From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [PATCH 2/2 v5] KVM: PPC: booke: Add watchdog emulation Date: Wed, 25 Jul 2012 21:46:43 -0300 Message-ID: <20120726004643.GA3904@amt.cnet> References: <1342760428-10858-1-git-send-email-Bharat.Bhushan@freescale.com> <5009CDA4.3080004@freescale.com> <20120725203708.GA31840@amt.cnet> <50108764.2070906@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Bharat Bhushan , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org, agraf@suse.de, Bharat Bhushan To: Scott Wood Return-path: Content-Disposition: inline In-Reply-To: <50108764.2070906@freescale.com> Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Wed, Jul 25, 2012 at 06:55:16PM -0500, Scott Wood wrote: > On 07/25/2012 03:37 PM, Marcelo Tosatti wrote: > > On Fri, Jul 20, 2012 at 04:29:08PM -0500, Scott Wood wrote: > >> On 07/20/2012 12:00 AM, Bharat Bhushan wrote: > >>> This patch adds the watchdog emulation in KVM. The watchdog > >>> emulation is enabled by KVM_ENABLE_CAP(KVM_CAP_PPC_WDT) ioctl. > >>> The kernel timer are used for watchdog emulation and emulates > >>> h/w watchdog state machine. On watchdog timer expiry, it exit to QEMU > >>> if TCR.WRC is non ZERO. QEMU can reset/shutdown etc depending upon how > >>> it is configured. > > > > Why can't you do this in QEMU, given the kernel exits to userspace on > > timer configuration? > > > > The QEMU timer handler used to emulate the watchdog then would have to > > only read the register value from the vCPU. > > Do what specifically in QEMU? The whole watchdog mechanism? > > It's only on final (third) expiry, when a reset is needed, that it exits > to QEMU. The first expiry sets a bit in TSR that software can clear to > clear the watchdog. If software doesn't clear it, the second expiry > sets a different bit in TSR that triggers a critical interrupt to the > guest. If software doesn't clear either of those bits by the time it > expires again, it's reset time (if a reset action is enabled). > > The TSR/TCR registers are shared with other timers that are implemented > in the kernel, and it would be more complicated to implement just the > watchdog in QEMU. Plus, we currently have no interface for exiting to > QEMU for emulation of an SPR. > > Currently QEMU on PPC leaves all timekeeping stuff to the kernel, and > I'd like to keep it that way. > > -Scott > OK.