From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v4 08/14] KVM: ARM: World-switch implementation Date: Fri, 30 Nov 2012 17:14:21 +0000 Message-ID: <20121130171420.GC619@mudshark.cambridge.arm.com> References: <20121110154203.2836.46686.stgit@chazy-air> <20121110154306.2836.93473.stgit@chazy-air> <20121119145758.GA3205@mudshark.cambridge.arm.com> <20121130151500.GC26289@mudshark.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "kvm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.cs.columbia.edu" , Marc Zyngier , Antonios Motakis , Marcelo Tosatti , Rusty Russell To: Christoffer Dall Return-path: Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:56240 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750854Ab2K3ROt (ORCPT ); Fri, 30 Nov 2012 12:14:49 -0500 Content-Disposition: inline In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: On Fri, Nov 30, 2012 at 04:47:40PM +0000, Christoffer Dall wrote: > On Fri, Nov 30, 2012 at 10:15 AM, Will Deacon wrote: > > At this point, VM1 is running and VM0:VCPU1 is running. VM0:VCPU0 is not > > running because physical CPU0 is handling an interrupt. The problem is that > > when VCPU0 *is* resumed, it will update the VMID of VM0 and could be > > scheduled in parallel with VCPU1 but with a different VMID. > > > > How do you avoid this in the current code? > > > I don't. Nice catch. Please apply your interesting brain to the following fix:) I'm far too sober to look at your patch right now, but I'll think about it over the weekend [I can't break it at a quick glance] :) In the meantime, can you think about whether the TLB operations need to run on every CPU please? Will