From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs Date: Fri, 30 Nov 2012 18:39:58 -0200 Message-ID: <20121130203958.GB22662@amt.cnet> References: <1353994338.31363.15.camel@WillAuldHomeLinux> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "jinsong.liu@intel.com" , Gleb , "kvm@vger.kernel.org" , qemu-devel , "donald.d.dugger@intel.com" , "avi@redhat.com" , Andreas Farber To: will.auld@intel.com Return-path: Content-Disposition: inline In-Reply-To: <1353994338.31363.15.camel@WillAuldHomeLinux> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org Sender: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org List-Id: kvm.vger.kernel.org On Mon, Nov 26, 2012 at 09:32:18PM -0800, Will Auld wrote: > CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported > > Basic design is to emulate the MSR by allowing reads and writes to the > hypervisor vcpu specific locations to store the value of the emulated MSRs. > In this way the IA32_TSC_ADJUST value will be included in all reads to > the TSC MSR whether through rdmsr or rdtsc. > > As this is a new MSR that the guest may access and modify its value needs > to be migrated along with the other MRSs. The changes here are specifically > for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added > for migrating its value. > > Signed-off-by: Will Auld > --- > Andreas, > > Thanks, that helped. I used Stefan's auto-run method this time. > > Will > > target-i386/cpu.h | 2 ++ > target-i386/kvm.c | 14 ++++++++++++++ > target-i386/machine.c | 21 +++++++++++++++++++++ > 3 files changed, 37 insertions(+) Applied, thanks.