From mboxrd@z Thu Jan  1 00:00:00 1970
From: Gleb Natapov <gleb@redhat.com>
Subject: Re: [PATCH v7 2/3] x86, apicv: add virtual interrupt delivery support
Date: Thu, 27 Dec 2012 08:38:36 +0200
Message-ID: <20121227063835.GM17584@redhat.com>
References: <1355722250-7122-1-git-send-email-yang.z.zhang@intel.com>
 <1355722250-7122-3-git-send-email-yang.z.zhang@intel.com>
 <20121220220042.GA14498@amt.cnet>
 <A9667DDFB95DB7438FA9D7D576C3D87E2EB1FB@SHSMSX101.ccr.corp.intel.com>
 <20121227062049.GK17584@redhat.com>
 <A9667DDFB95DB7438FA9D7D576C3D87E2EB314@SHSMSX101.ccr.corp.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Cc: Marcelo Tosatti <mtosatti@redhat.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"Shan, Haitao" <haitao.shan@intel.com>,
	"Tian, Kevin" <kevin.tian@intel.com>
To: "Zhang, Yang Z" <yang.z.zhang@intel.com>
Return-path: <kvm-owner@vger.kernel.org>
Received: from mx1.redhat.com ([209.132.183.28]:28608 "EHLO mx1.redhat.com"
	rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP
	id S1750870Ab2L0Gii (ORCPT <rfc822;kvm@vger.kernel.org>);
	Thu, 27 Dec 2012 01:38:38 -0500
Content-Disposition: inline
In-Reply-To: <A9667DDFB95DB7438FA9D7D576C3D87E2EB314@SHSMSX101.ccr.corp.intel.com>
Sender: kvm-owner@vger.kernel.org
List-ID: <kvm.vger.kernel.org>

On Thu, Dec 27, 2012 at 06:34:37AM +0000, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2012-12-27:
> > On Thu, Dec 27, 2012 at 03:32:47AM +0000, Zhang, Yang Z wrote:
> >> Marcelo Tosatti wrote on 2012-12-21:
> >>> On Mon, Dec 17, 2012 at 01:30:49PM +0800, Yang Zhang wrote:
> >>>> From: Yang Zhang <yang.z.zhang@Intel.com>
> >>>> 
> >>>> @@ -3925,6 +3942,15 @@ static int vmx_vcpu_setup(struct vcpu_vmx
> > *vmx)
> >>>>  				vmx_secondary_exec_control(vmx));
> >>>>  	}
> >>>> +	if (enable_apicv_reg_vid) {
> >>>> +		vmcs_write64(EOI_EXIT_BITMAP0, 0);
> >>>> +		vmcs_write64(EOI_EXIT_BITMAP1, 0);
> >>>> +		vmcs_write64(EOI_EXIT_BITMAP2, 0);
> >>>> +		vmcs_write64(EOI_EXIT_BITMAP3, 0);
> >>>> +
> >>>> +		vmcs_write16(GUEST_INTR_STATUS, 0);
> >>>> +	}
> >>> 
> >>> AFAICS SVI should be regenerated on migration. Consider:
> >>> 
> >>> 1. vintr delivery, sets SVI = vector = RVI.
> >>> 2. clears RVI.
> >>> 3. migration.
> >>> 4. RVI properly set from VIRR on entry.
> >>> 5. SVI = 0.
> >>> 6. EOI -> EOI virtualization with SVI = 0.
> >>> 
> >>> Could hook into kvm_apic_post_state_restore() to do that (set highest
> >>> index of bit set in VISR).
> >> Ok. How about to make a request(KVM_REQ_UPDATE_SVI) and handle it in
> >> vmentry to set highest index of bit in VISR to RVI.
> >> 
> > Just do it in kvm_apic_post_state_restore() directly, no need to do
> > a request.
> What you mean "do it directly". Since we are not in target vcpu's context, we cannot access vmcs at this point. We still need a request or variable to indicate the migration happened.
> 
We are in a target vcpu context.

--
			Gleb.