From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gleb Natapov Subject: Re: in-kernel interrupt controller steering Date: Wed, 6 Mar 2013 15:56:05 +0200 Message-ID: <20130306135605.GA13471@redhat.com> References: <469599439.3185295.1362572055225.JavaMail.root@redhat.com> <1777B6DD-B341-4531-BE43-7B0161B1D093@suse.de> <20130306131424.GR11223@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Paolo Bonzini , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Stuart Yoder , Scott Wood , Paul Mackerras , Peter Maydell To: Alexander Graf Return-path: Content-Disposition: inline In-Reply-To: Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Wed, Mar 06, 2013 at 02:22:15PM +0100, Alexander Graf wrote: > > On 06.03.2013, at 14:14, Gleb Natapov wrote: > > > On Wed, Mar 06, 2013 at 01:20:39PM +0100, Alexander Graf wrote: > >>> The problem would only start if KVM_SET_IRQCHIP_TYPE (new name of > >>> KVM_CREATE_IRQCHIP_ARGS) forced you to later call KVM_CREATE_DEVICE. > >> > >> Ah, I see. I don't see why it would. The fact that there is a "LAPIC" doesn't mean that the per-vcpu SET_INTERRUPT ioctl stops working. So if SET_IRQCHIP_TYPE(!none) breaks user-space interrupt controller emulation I would consider that a bug. > >> > > For x86 this is the case though. I do not see how it can't be. If > > LAPIC is emulated in userspace SET_INTERRUPT is used to pass IRQ > > vector that should be handled as a result of LAPIC emulation. > > So SET_INTERRUPT on a vcpu triggers a line on the LAPIC emulation in that vcpu? For us it directly controls the CPU interrupt pin. > No SET_INTERRUPT on a vcpu tells vcpu to which vector in IDT it needs to jump immediately. LAPIC is really part of a cpu and we cut it and put into userspace, so interface between userspace LAPIC emulation is really low level and has to be synchronous. X86 has two interrupt lines NMI and INTR and we do not have interface to trigger the later. KVM_IRQ_LINE works on GSI lines which do not go into CPU directly. They go either via PIC (which triggers INTR or APIC LINT0) or via IOAPIC which on real HW communicates with APICs via bus, but in our emulation just calls APICs directly. -- Gleb.