From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Mackerras Subject: Re: in-kernel interrupt controller steering Date: Thu, 7 Mar 2013 11:32:46 +1100 Message-ID: <20130307003246.GA2385@drongo> References: <469599439.3185295.1362572055225.JavaMail.root@redhat.com> <1777B6DD-B341-4531-BE43-7B0161B1D093@suse.de> <20130306131424.GR11223@redhat.com> <20130306135605.GA13471@redhat.com> <8A2E7B22-8933-42CF-AD7D-6AC27F1E4B1F@suse.de> <20130306144115.GT11223@redhat.com> <3EEF9BBC-9C40-45CE-9705-5F6D26CC50B6@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Gleb Natapov , Paolo Bonzini , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Stuart Yoder , Scott Wood , Peter Maydell To: Alexander Graf Return-path: Content-Disposition: inline In-Reply-To: <3EEF9BBC-9C40-45CE-9705-5F6D26CC50B6@suse.de> Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Wed, Mar 06, 2013 at 03:48:54PM +0100, Alexander Graf wrote: > > Paul, Scott, do you think we can move the "this CPU can receive > interrupts from MPIC / XICS" part into an ENABLE_CAP that gets set > dynamically? That ENABLE_CAP would allocate the structures in the vcpu > and register the vcpu with the interrupt controller pool. > > The interrupt controller device would still iterate through all > vcpus to find the ones that match so that we support the ENABLE_CAP at > any point in time. When you say "gets set dynamically", do you mean some time in the interval between vcpu creation and when it starts running, or do you mean at any time, potentially after the vcpu has accessed and modified its per-vcpu interrupt controller (~ LAPIC) state? If the former, then sure, I don't see a major problem. If the latter, then we'd have to atomically transfer the "LAPIC" state from userspace to the kernel at the same time as we did the ENABLE_CAP - which is certainly possible, but we'd need the vcpu to be not running at the time. Paul.