From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v3 08/32] arm64: KVM: architecture specific MMU backend Date: Wed, 24 Apr 2013 12:10:02 +0100 Message-ID: <20130424111002.GJ21850@mudshark.cambridge.arm.com> References: <1365437854-30214-1-git-send-email-marc.zyngier@arm.com> <1365437854-30214-9-git-send-email-marc.zyngier@arm.com> <20130423225816.GC20569@gmail.com> <5177BBEE.1090209@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Christoffer Dall , "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.cs.columbia.edu" , "kvm@vger.kernel.org" , Catalin Marinas , Christopher Covington To: Marc Zyngier Return-path: Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:39489 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753990Ab3DXLKZ (ORCPT ); Wed, 24 Apr 2013 07:10:25 -0400 Content-Disposition: inline In-Reply-To: <5177BBEE.1090209@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, Apr 24, 2013 at 12:03:10PM +0100, Marc Zyngier wrote: > On 23/04/13 23:58, Christoffer Dall wrote: > > I noticed that this doesn't do any cache cleaning. Are the MMU page > > table walks guaranteed to be coherent with the MMU on arm64? > > I suppose you meant the cache. In this case, yes. The hardware page > table walker must snoop the caches. Also, for ARMv7, SMP implies that the hardware walker snoops the cache. I recently upstreamed some patches for this (see "ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead" in -next), so you might want to check if there are any remaining, redundant flushes in kvm for ARMv7. Will