From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [PATCH v3 07/15] KVM: MMU: introduce nulls desc Date: Thu, 5 Dec 2013 22:15:54 -0200 Message-ID: <20131206001554.GA28698@amt.cnet> References: <20131122191429.GA13308@amt.cnet> <65EE805B-B5DB-4BD0-A057-E5FF78D96D67@linux.vnet.ibm.com> <5292EE2F.5090305@linux.vnet.ibm.com> <20131125181254.GB21858@amt.cnet> <529413C1.60302@linux.vnet.ibm.com> <20131126193148.GA18071@amt.cnet> <5297049E.3020800@linux.vnet.ibm.com> <529D83F8.7050605@linux.vnet.ibm.com> <20131205135021.GA12996@amt.cnet> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Gleb Natapov , avi.kivity@gmail.com, "pbonzini@redhat.com Bonzini" , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Eric Dumazet , Peter Zijlstra To: Xiao Guangrong Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Thu, Dec 05, 2013 at 11:30:27PM +0800, Xiao Guangrong wrote: > > Is it not the case that simply moving to the slow path once a maxim= um of > > rewalks has been reached enough? (looks a like a good solution). >=20 > In some cases, the lockless walker will do endless-walking on desc an= d > without rewalk, consider this case: >=20 > there are two descs: desc1 and desc2 who is pointed by desc1->next=EF= =BC=9A > desc1->next =3D desc2. >=20 > CPU 0 = CPU 1 >=20 > lockless walk on desc1 > dele= ting desc1 from the rmap > lockless walk on desc2 (desc1->next) > delet= e desc2 from the rmap > add d= esc1 > add d= esc2, then desc2->next =3D desc1 >=20 > lockless walk on desc1 > delete= desc2 > delete= desc1 > add de= sc2 > add de= sc1; the desc1->next =3D desc2 > lockless walk on desc2 >=20 > =E2=80=A6=E2=80=A6 >=20 > Then, the walker is endlessly walking on desc1 and desc2 without any = rewalk. Ouch, this is the sort of thing that is worrysome. Do you still think that having the benefit for shadow is important enough to justify this complexity? Also, another separate possibility is to use the dirty bit (which recen= t Intel processors support). Then there are no faults at all to handle.