From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: "Liang, Kan" <kan.liang@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"Kleen, Andi" <andi.kleen@intel.com>
Subject: Re: [PATCH 1/2] perf: ignore LBR and offcore_rsp.
Date: Mon, 23 Jun 2014 11:19:52 +0200 [thread overview]
Message-ID: <20140623091952.GP19860@laptop.programming.kicks-ass.net> (raw)
In-Reply-To: <87ha3g947f.fsf@tassilo.jf.intel.com>
On Thu, Jun 19, 2014 at 10:52:52AM -0700, Andi Kleen wrote:
> Andi Kleen <andi@firstfloor.org> writes:
> >>
> >>> Signed-off-by: Kan Liang <kan.liang@intel.com>
> >>
> >> And here I thought that Andi was of the opinion that if you set CPUID to
> >> indicate a particular CPU you had better also handle all its MSRs.
> >
> > Yes, philosophically that would be the right way,
> > but we needed a short term fix to stop things from crashing, and that
> > was the simplest.
>
> I should add there is another reason for this patch now,
> and doing it in perf instead of somewhere else
> (this should probably go into the description).
>
> With PT on enabling LBR can #GP. So perf needs to handle
> this case without crashing. This can happen independently
> of any hypervisors.
WTH is a PT?
next prev parent reply other threads:[~2014-06-23 9:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <37D7C6CF3E00A74B8858931C1DB2F0770148F513@SHSMSX103.ccr.corp.intel.com>
2014-06-18 15:59 ` [PATCH 1/2] perf: ignore LBR and offcore_rsp Peter Zijlstra
2014-06-18 16:04 ` Andi Kleen
2014-06-19 17:52 ` Andi Kleen
2014-06-23 9:19 ` Peter Zijlstra [this message]
2014-06-23 9:29 ` Peter Zijlstra
2014-06-23 15:56 ` Andi Kleen
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