From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [patch 2/5] KVM: MMU: allow pinning spte translations (TDP-only) Date: Mon, 30 Jun 2014 17:46:46 -0300 Message-ID: <20140630204646.GA26566@amt.cnet> References: <20140618231203.846608908@amt.cnet> <20140618231521.569025131@amt.cnet> <20140619072116.GC10948@minantech.com> <20140619192257.GA5561@amt.cnet> <20140620100911.GB20764@minantech.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: kvm@vger.kernel.org, ak@linux.intel.com, pbonzini@redhat.com, xiaoguangrong@linux.vnet.ibm.com, avi@cloudius-systems.com To: Gleb Natapov , ak@linux.intel.com Return-path: Received: from mx1.redhat.com ([209.132.183.28]:60861 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750800AbaF3UrJ (ORCPT ); Mon, 30 Jun 2014 16:47:09 -0400 Content-Disposition: inline In-Reply-To: <20140620100911.GB20764@minantech.com> Sender: kvm-owner@vger.kernel.org List-ID: On Fri, Jun 20, 2014 at 01:09:12PM +0300, Gleb Natapov wrote: > On Thu, Jun 19, 2014 at 04:22:57PM -0300, Marcelo Tosatti wrote: > > On Thu, Jun 19, 2014 at 10:21:16AM +0300, Gleb Natapov wrote: > > > On Wed, Jun 18, 2014 at 08:12:05PM -0300, mtosatti@redhat.com wrote: > > > > Allow vcpus to pin spte translations by: > > > > > > > > 1) Creating a per-vcpu list of pinned ranges. > > > What if memory slot containing pinned range is going away? > > > > ->page_fault() should fail and guest abort. Will double check. > > > > > > 2) On mmu reload request: > > > > - Fault ranges. > > > > - Mark sptes with a pinned bit. > > > Should also be marked "dirty" as per SDM: > > > The three DS save area sections should be allocated from a non-paged pool, and marked accessed and dirty > > > > This (SDM text) is about guest pagetable AFAICS. > > > Its hard to say. SDM does not mention virtualization or two dimensional > paging in that section at all. My reading is that this section talks about > all translations that CPU should perform to get to the physical address, > otherwise why are we trying hard to make sure that EPT translations are > always present? Because the same paragraph say in the next sentence: > > It is the responsibility of the operating system to keep the pages that > contain the buffer present and to mark them accessed and dirty > > So it we take from it that translation should be present the same goes for > accessed and dirty. If Andi can clarify this within Intel it would be great. Andi?