From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andi Kleen Subject: Re: [PATCH V2 1/3] perf ignore LBR and offcore_rsp. Date: Wed, 2 Jul 2014 19:16:06 -0700 Message-ID: <20140703021606.GT19781@tassilo.jf.intel.com> References: <1404324855-15166-1-git-send-email-kan.liang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: peterz@infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, andi@firstfloor.org To: kan.liang@intel.com Return-path: Content-Disposition: inline In-Reply-To: <1404324855-15166-1-git-send-email-kan.liang@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org > Signed-off-by: Andi Kleen I did not contribute to this patch, so please remove that SOB. > Signed-off-by: Kan Liang > struct extra_reg *extra_regs; > unsigned int er_flags; > + bool extra_msr_access; /* EXTRA REG MSR can be accessed */ > This doesn't look right, needs a flag for each extra register. They are completely unrelated to each other. BTW this will also cause KVM messages at each boot now. > wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); > wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); > } > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c > index adb02aa..8011d42 100644 > --- a/arch/x86/kernel/cpu/perf_event_intel.c > +++ b/arch/x86/kernel/cpu/perf_event_intel.c > @@ -2565,6 +2565,13 @@ __init int intel_pmu_init(void) > } > } > > + /* Access LBR MSR may cause #GP under certain circumstances. E.g. KVM doesn't support LBR MSR */ > + if (x86_pmu.lbr_nr) > + x86_pmu.lbr_msr_access = test_msr_access(x86_pmu.lbr_tos) & test_msr_access(x86_pmu.lbr_from); s/&/&&/ And also this doesn't cover the case when someone takes over the LBRs and they start #GPing later. So for LBR the test has to be still at each access. -Andi