Re: [PATCH V3 1/2] perf ignore LBR and offcore_rsp.

[Peter Zijlstra <peterz@infradead.org>]

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On Mon, Jul 07, 2014 at 06:34:25AM -0700, kan.liang@intel.com wrote:
> @@ -555,7 +577,11 @@ static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
>  {
>  	u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
>  
> -	if (hwc->extra_reg.reg)
> +	if (hwc->extra_reg.reg &&
> +		((hwc->extra_reg.idx == EXTRA_REG_RSP_0) ?
> +			x86_pmu.extra_msr_access[0] : true) &&
> +		((hwc->extra_reg.idx == EXTRA_REG_RSP_1) ?
> +			x86_pmu.extra_msr_access[1] : true))
>  		wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
>  	wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
>  }

> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index adb02aa..3d18765 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c

> +	/*
> +	 * Access extra MSR may cause #GP under certain circumstances.
> +	 * E.g. KVM doesn't support offcore event
> +	 * Check all extra_regs here.
> +	 */
> +	if (x86_pmu.extra_regs) {
> +		x86_pmu.extra_msr_access[0] =
> +			check_msr(x86_pmu.extra_regs[EXTRA_REG_RSP_0].msr);
> +
> +		/* Not all platforms have EXTRA_REG_RSP_1 */
> +		if (x86_pmu.extra_regs[EXTRA_REG_RSP_1].idx == EXTRA_REG_RSP_1)
> +			x86_pmu.extra_msr_access[1] =
> +			check_msr(x86_pmu.extra_regs[EXTRA_REG_RSP_1].msr);
> +		/*
> +		 * If there is no EXTRA_REG_RSP_1 support,
> +		 * just set the flag to be true.
> +		 * So it is ignored at the runtime check.
> +		 */
> +		else
> +			x86_pmu.extra_msr_access[1] = true;
> +	}

This too is wrong in many ways; there's more than 2 extra_msrs on many
systems.

And the place you check is abysmal, if we know at init time that we
don't have those MSRs, WTF do you allow event creation that would use
them, only to then misbehave?

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