Re: [PATCH] KVM-Use value reading from MSR when construct the eptp in VMX mode

Re: [PATCH] KVM-Use value reading from MSR when construct the eptp in VMX mode

[Wanpeng Li]

Please Cc kvm ml.
On Sun, Aug 24, 2014 at 11:54:32AM +0800, Dennis Chen wrote:
>This patch is used to construct the eptp in vmx mode with values
>readed from MSR according to the intel x86 software developer's
>manual.
>
>Signed-off-by: Dennis Chen <kernel.org.gnu@gmail.com>
>---
> arch/x86/include/asm/vmx.h |    1 +
> arch/x86/kvm/vmx.c         |   21 +++++++++++++++++----
> 2 files changed, 18 insertions(+), 4 deletions(-)
>
>diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
>index bcbfade..bf82a77 100644
>--- a/arch/x86/include/asm/vmx.h
>+++ b/arch/x86/include/asm/vmx.h
>@@ -417,6 +417,7 @@ enum vmcs_field {
> #define VMX_EPT_GAW_EPTP_SHIFT            3
> #define VMX_EPT_AD_ENABLE_BIT            (1ull << 6)
> #define VMX_EPT_DEFAULT_MT            0x6ull
>+#define VMX_EPT_UC_MT                0x0ull
> #define VMX_EPT_READABLE_MASK            0x1ull
> #define VMX_EPT_WRITABLE_MASK            0x2ull
> #define VMX_EPT_EXECUTABLE_MASK            0x4ull
>diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>index bfe11cf..7add5ce 100644
>--- a/arch/x86/kvm/vmx.c
>+++ b/arch/x86/kvm/vmx.c
>@@ -3477,11 +3477,24 @@ static void vmx_set_cr0(struct kvm_vcpu *vcpu,
>unsigned long cr0)
>
> static u64 construct_eptp(unsigned long root_hpa)
> {
>-    u64 eptp;
>+    u64 eptp, pwl;
>+
>+    if (cpu_has_vmx_ept_4levels())
>+        pwl = VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>+    else {
>+        WARN(1, "Unsupported page-walk length of 4.\n");
>+        BUG();
>+    }
>+
>+    if (cpu_has_vmx_eptp_writeback())
>+        eptp = VMX_EPT_DEFAULT_MT | pwl;
>+    else if (cpu_has_vmx_eptp_uncacheable())
>+        eptp = VMX_EPT_UC_MT | pwl;
>+    else {
>+        WARN(1, "Unsupported memory type config in vmx eptp.\n");
>+        BUG();
>+    }
>
>-    /* TODO write the value reading from MSR */
>-    eptp = VMX_EPT_DEFAULT_MT |
>-        VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>     if (enable_ept_ad_bits)
>         eptp |= VMX_EPT_AD_ENABLE_BIT;
>     eptp |= (root_hpa & PAGE_MASK);
>-- 
>1.7.9.5

Re: [PATCH] KVM-Use value reading from MSR when construct the eptp in VMX mode

[Dennis Chen]

On Mon, Aug 25, 2014 at 7:14 AM, Wanpeng Li <wanpeng.li@linux.intel.com> wrote:
> Please Cc kvm ml.

You've done that for me, thanks. The page-walk length sanity check has
been done in the hardware_setup() function, so it's not necessary in
this patch, but I still think it does make sense for the memory type
check, any comments, guys?

> On Sun, Aug 24, 2014 at 11:54:32AM +0800, Dennis Chen wrote:
>>This patch is used to construct the eptp in vmx mode with values
>>readed from MSR according to the intel x86 software developer's
>>manual.
>>
>>Signed-off-by: Dennis Chen <kernel.org.gnu@gmail.com>
>>---
>> arch/x86/include/asm/vmx.h |    1 +
>> arch/x86/kvm/vmx.c         |   21 +++++++++++++++++----
>> 2 files changed, 18 insertions(+), 4 deletions(-)
>>
>>diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
>>index bcbfade..bf82a77 100644
>>--- a/arch/x86/include/asm/vmx.h
>>+++ b/arch/x86/include/asm/vmx.h
>>@@ -417,6 +417,7 @@ enum vmcs_field {
>> #define VMX_EPT_GAW_EPTP_SHIFT            3
>> #define VMX_EPT_AD_ENABLE_BIT            (1ull << 6)
>> #define VMX_EPT_DEFAULT_MT            0x6ull
>>+#define VMX_EPT_UC_MT                0x0ull
>> #define VMX_EPT_READABLE_MASK            0x1ull
>> #define VMX_EPT_WRITABLE_MASK            0x2ull
>> #define VMX_EPT_EXECUTABLE_MASK            0x4ull
>>diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>>index bfe11cf..7add5ce 100644
>>--- a/arch/x86/kvm/vmx.c
>>+++ b/arch/x86/kvm/vmx.c
>>@@ -3477,11 +3477,24 @@ static void vmx_set_cr0(struct kvm_vcpu *vcpu,
>>unsigned long cr0)
>>
>> static u64 construct_eptp(unsigned long root_hpa)
>> {
>>-    u64 eptp;
>>+    u64 eptp, pwl;
>>+
>>+    if (cpu_has_vmx_ept_4levels())
>>+        pwl = VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>>+    else {
>>+        WARN(1, "Unsupported page-walk length of 4.\n");
>>+        BUG();
>>+    }
>>+
>>+    if (cpu_has_vmx_eptp_writeback())
>>+        eptp = VMX_EPT_DEFAULT_MT | pwl;
>>+    else if (cpu_has_vmx_eptp_uncacheable())
>>+        eptp = VMX_EPT_UC_MT | pwl;
>>+    else {
>>+        WARN(1, "Unsupported memory type config in vmx eptp.\n");
>>+        BUG();
>>+    }
>>
>>-    /* TODO write the value reading from MSR */
>>-    eptp = VMX_EPT_DEFAULT_MT |
>>-        VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>>     if (enable_ept_ad_bits)
>>         eptp |= VMX_EPT_AD_ENABLE_BIT;
>>     eptp |= (root_hpa & PAGE_MASK);
>>--
>>1.7.9.5

Re: [PATCH] KVM-Use value reading from MSR when construct the eptp in VMX mode

[Dennis Chen]

On Sun, Aug 24, 2014 at 5:38 PM, Gleb Natapov <gleb@kernel.org> wrote:
> On Sun, Aug 24, 2014 at 11:54:32AM +0800, Dennis Chen wrote:
>> This patch is used to construct the eptp in vmx mode with values
>> readed from MSR according to the intel x86 software developer's
>> manual.
>>
>>  static u64 construct_eptp(unsigned long root_hpa)
>>  {
>> -    u64 eptp;
>> +    u64 eptp, pwl;
>> +
>> +    if (cpu_has_vmx_ept_4levels())
>> +        pwl = VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>> +    else {
>> +        WARN(1, "Unsupported page-walk length of 4.\n");
> Page-walk length of 4 is the only one that is supported.
>
Since there is a bit 6 in IA32_VMX_EPT_VPID_CAP MSR indicating the
support for the page-walk length, I think sanity check is necessary.
But I just checked the code, it's already done in the hardware_setup()
function which will disable ept feature if the page-wake length is not
4. Gleb, any comments for the memory type check part?

>> +        BUG();
>> +    }
>> +
>> +    if (cpu_has_vmx_eptp_writeback())
>> +        eptp = VMX_EPT_DEFAULT_MT | pwl;
>> +    else if (cpu_has_vmx_eptp_uncacheable())
>> +        eptp = VMX_EPT_UC_MT | pwl;
>> +    else {
>> +        WARN(1, "Unsupported memory type config in vmx eptp.\n");
>> +        BUG();
>> +    }
>>
>> -    /* TODO write the value reading from MSR */
>> -    eptp = VMX_EPT_DEFAULT_MT |
>> -        VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>>      if (enable_ept_ad_bits)
>>          eptp |= VMX_EPT_AD_ENABLE_BIT;
>>      eptp |= (root_hpa & PAGE_MASK);
>> --
>> 1.7.9.5
>
> --
>                         Gleb.

Re: [PATCH] KVM-Use value reading from MSR when construct the eptp in VMX mode

[Gleb Natapov]

On Mon, Aug 25, 2014 at 11:16:34AM +0800, Dennis Chen wrote:
> On Sun, Aug 24, 2014 at 5:38 PM, Gleb Natapov <gleb@kernel.org> wrote:
> > On Sun, Aug 24, 2014 at 11:54:32AM +0800, Dennis Chen wrote:
> >> This patch is used to construct the eptp in vmx mode with values
> >> readed from MSR according to the intel x86 software developer's
> >> manual.
> >>
> >>  static u64 construct_eptp(unsigned long root_hpa)
> >>  {
> >> -    u64 eptp;
> >> +    u64 eptp, pwl;
> >> +
> >> +    if (cpu_has_vmx_ept_4levels())
> >> +        pwl = VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
> >> +    else {
> >> +        WARN(1, "Unsupported page-walk length of 4.\n");
> > Page-walk length of 4 is the only one that is supported.
> >
> Since there is a bit 6 in IA32_VMX_EPT_VPID_CAP MSR indicating the
> support for the page-walk length, I think sanity check is necessary.
> But I just checked the code, it's already done in the hardware_setup()
> function which will disable ept feature if the page-wake length is not
> 4. Gleb, any comments for the memory type check part?
Looks fine, but are there CPUs out there that do not support WB for eptp? Since
there was no bug reports about it I assume no.

--
			Gleb.

Re: [PATCH] KVM-Use value reading from MSR when construct the eptp in VMX mode

[Dennis Chen]

On Mon, Aug 25, 2014 at 10:04 PM, Gleb Natapov <gleb@kernel.org> wrote:
> On Mon, Aug 25, 2014 at 11:16:34AM +0800, Dennis Chen wrote:
>> On Sun, Aug 24, 2014 at 5:38 PM, Gleb Natapov <gleb@kernel.org> wrote:
>> > On Sun, Aug 24, 2014 at 11:54:32AM +0800, Dennis Chen wrote:
>> >> This patch is used to construct the eptp in vmx mode with values
>> >> readed from MSR according to the intel x86 software developer's
>> >> manual.
>> >>
>> >>  static u64 construct_eptp(unsigned long root_hpa)
>> >>  {
>> >> -    u64 eptp;
>> >> +    u64 eptp, pwl;
>> >> +
>> >> +    if (cpu_has_vmx_ept_4levels())
>> >> +        pwl = VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>> >> +    else {
>> >> +        WARN(1, "Unsupported page-walk length of 4.\n");
>> > Page-walk length of 4 is the only one that is supported.
>> >
>> Since there is a bit 6 in IA32_VMX_EPT_VPID_CAP MSR indicating the
>> support for the page-walk length, I think sanity check is necessary.
>> But I just checked the code, it's already done in the hardware_setup()
>> function which will disable ept feature if the page-wake length is not
>> 4. Gleb, any comments for the memory type check part?
> Looks fine, but are there CPUs out there that do not support WB for eptp? Since
> there was no bug reports about it I assume no.

Hmm, currently I can't find a x86 processor that don't support WB for
eptp, also there is no relevant bug reported.
I just read the intel SDM 24.6.11: SW should read the VMX capability
MSR_IA32_VMX_EPT_VPID_CAP to determine
what EPT MT are supported. But looks like this is not a big concern in
the community, so let's go back this thread if
we encounter one unfornately in the future. Thanks for the comments.

>
> --
>                         Gleb.



-- 
Den