From mboxrd@z Thu Jan  1 00:00:00 1970
From: Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [PATCH 4/4] arm/arm64: KVM: use kernel mapping to perform
 invalidation on page fault
Date: Tue, 13 Jan 2015 14:35:16 +0100
Message-ID: <20150113133516.GF26222@cbox>
References: <20150111123347.GV21092@cbox>
 <CAFEAcA8cYMnotQTs16hcZtcup_A3az68_r2QTwUsG8f9G+gWBA@mail.gmail.com>
 <20150111175841.GI21444@cbox>
 <CAFEAcA9kPPe9n0q5bQ5PQ1BgLMeyHUiNgQSOpuvSN=wefAEFLQ@mail.gmail.com>
 <20150111183828.GA3868@cbox>
 <54B39AC6.7000807@arm.com>
 <20150112201009.GC26222@cbox>
 <54B503CE.4000809@arm.com>
 <20150113120458.GE26222@cbox>
 <CAFEAcA_DqJnW83uLMTJGiKLzOQp3HV6Ab3A1wfncpJ7E0UxgSw@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	kvm-devel <kvm@vger.kernel.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>
To: Peter Maydell <peter.maydell@linaro.org>
Return-path: <kvm-owner@vger.kernel.org>
Received: from mail-la0-f44.google.com ([209.85.215.44]:39078 "EHLO
	mail-la0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
	with ESMTP id S1751240AbbAMNfS (ORCPT <rfc822;kvm@vger.kernel.org>);
	Tue, 13 Jan 2015 08:35:18 -0500
Received: by mail-la0-f44.google.com with SMTP id gd6so2634281lab.3
        for <kvm@vger.kernel.org>; Tue, 13 Jan 2015 05:35:17 -0800 (PST)
Content-Disposition: inline
In-Reply-To: <CAFEAcA_DqJnW83uLMTJGiKLzOQp3HV6Ab3A1wfncpJ7E0UxgSw@mail.gmail.com>
Sender: kvm-owner@vger.kernel.org
List-ID: <kvm.vger.kernel.org>

On Tue, Jan 13, 2015 at 12:12:41PM +0000, Peter Maydell wrote:
> On 13 January 2015 at 12:04, Christoffer Dall
> <christoffer.dall@linaro.org> wrote:
> > Additionally, I haven't been able to think of a reasonable guest
> > scenario where this breaks.  Once the guest turns on its MMU it should
> > deal with the necessary icache invalidation itself (I think), so we're
> > really talking about situations where the stage-1 MMU is off, and I
> > gather that mostly you'll be seeing a single core doing any heavy
> > lifting and then secondary cores basically coming up, only seeing valid
> > entries in the icache, and doing the necessary invalidat+turn on mmu
> > stuff.
> 
> The trouble with that is that as the secondary comes up, before it
> turns on its icache its VA->PA mapping is the identity map; whereas
> the primary vCPU's VA->PA mapping is "whatever the guest kernel's
> usual mapping is". If the kernel has some mapping other than identity
> for the VA which is wherever the secondary-CPU-startup-to-MMU-enable
> code lives (which seems quite likely), then you have potential problems.
> 
Wouldn't a guest (and I believe Linux does this) reserve ASID 0 for
additional cores and use ASID 1+++ for itself?

Or does the potential hits in the icache for a stage-1 turned-off MMU
hit on all ASIDs ?

-Christoffer