From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcelo Tosatti Subject: Re: [PATCH RFC 0/9] Implement handling of RH=1 for MSI delivery in KVM Date: Mon, 16 Mar 2015 22:11:23 -0300 Message-ID: <20150317011123.GA6255@amt.cnet> References: <1426377624-2046-1-git-send-email-sullivan.james.f@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: kvm@vger.kernel.org, gleb@kernel.org, pbonzini@redhat.com To: James Sullivan Return-path: Received: from mx1.redhat.com ([209.132.183.28]:1466 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750933AbbCQBsN (ORCPT ); Mon, 16 Mar 2015 21:48:13 -0400 Content-Disposition: inline In-Reply-To: <1426377624-2046-1-git-send-email-sullivan.james.f@gmail.com> Sender: kvm-owner@vger.kernel.org List-ID: On Sat, Mar 14, 2015 at 06:00:15PM -0600, James Sullivan wrote: > This series of patches extends the KVM interrupt delivery mechanism > to correctly account for the MSI Redirection Hint bit. The RH bit is > used in logical destination mode to indicate that the delivery of the > interrupt shall only be to the lowest priority candidate LAPIC. > > Currently, there is no handling of the MSI RH bit in the KVM interrupt > delivery mechanism. This patch implements the following logic: > > * DM=0, RH=* : Physical destination mode. Interrupt is delivered to > the LAPIC with the matching APIC ID. (Subject to > the usual restrictions, i.e. no broadcast dest) > * DM=1, RH=0 : Logical destination mode without redirection. Interrupt > is delivered to all LAPICs in the logical group > specified by the IRQ's destination map and delivery > mode. "When RH is 0, the interrupt is directed to the processor listed in the Destination ID field." > * DM=1, RH=1 : Logical destination mode with redirection. Interrupt > is delivered only to the lowest priority LAPIC in the > logical group specified by the dest map and the > delivery mode. Delivery semantics are otherwise > specified by the delivery_mode of the IRQ, which > is unchanged. > > In other words, the RH bit is ignored in physical destination mode, and > when it is set in logical destination mode causes delivery to only apply > to the lowest priority processor in the logical group. The IA32 manual > is in slight contradiction with itself on this matter, but this patch > agrees with this interpretation of the RH bit: > > https://software.intel.com/en-us/forums/topic/288883 > > This patch has passed some rudimentary tests using an SMP QEMU guest and > virtio sourced MSIs, but I haven't done experiments with passing through > PCI hardware (intend to start working on this). > > Let me know your thoughts. > > -James > > -- > To unsubscribe from this list: send the line "unsubscribe kvm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html