From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoffer Dall Subject: Re: [PATCH v11 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Date: Mon, 8 Feb 2016 13:09:50 +0100 Message-ID: <20160208120950.GC620@cbox> References: <1454656456-11640-1-git-send-email-zhaoshenglong@huawei.com> <1454656456-11640-7-git-send-email-zhaoshenglong@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, will.deacon@arm.com, wei@redhat.com, cov@codeaurora.org, shannon.zhao@linaro.org, peter.huangpeng@huawei.com, hangaohuai@huawei.com To: Shannon Zhao Return-path: Received: from mail-wm0-f42.google.com ([74.125.82.42]:34012 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751183AbcBHMJP (ORCPT ); Mon, 8 Feb 2016 07:09:15 -0500 Received: by mail-wm0-f42.google.com with SMTP id 128so152166025wmz.1 for ; Mon, 08 Feb 2016 04:09:14 -0800 (PST) Content-Disposition: inline In-Reply-To: <1454656456-11640-7-git-send-email-zhaoshenglong@huawei.com> Sender: kvm-owner@vger.kernel.org List-ID: On Fri, Feb 05, 2016 at 03:14:01PM +0800, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which gets host value of PMCEID0 or PMCEID1 when > guest access these registers. Writing action to PMCEID0 or PMCEID1 is > UNDEFINED. > > Signed-off-by: Shannon Zhao > --- > arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++---- > 1 file changed, 25 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index fc60041..06257e2 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -492,6 +492,27 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > return true; > } > > +static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 pmceid; > + > + if (!kvm_arm_pmu_v3_ready(vcpu)) > + return trap_raz_wi(vcpu, p, r); > + > + if (p->is_write) > + return false; Isn't it really a BUG_ON(p->is_write) ? Presumably a guest write to these registers will raise an undefined exception in EL0/1 and we don't get here by any other path than the trap handler, do we? Otherwise looks good to me. Thanks, -Christoffer