From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoffer Dall Subject: Re: [PATCH 01/17] arm64: Reuse TCR field definitions for EL1 and EL2 Date: Fri, 8 Apr 2016 14:43:39 +0200 Message-ID: <20160408124339.GM8961@cbox> References: <1459787177-12767-1-git-send-email-suzuki.poulose@arm.com> <1459787177-12767-2-git-send-email-suzuki.poulose@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org To: Suzuki K Poulose Return-path: Content-Disposition: inline In-Reply-To: <1459787177-12767-2-git-send-email-suzuki.poulose@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu List-Id: kvm.vger.kernel.org On Mon, Apr 04, 2016 at 05:26:01PM +0100, Suzuki K Poulose wrote: > TCR_EL1, TCR_EL2 and VTCR_EL2, all share some field positions > (TG0, ORGN0, IRGN0 and SH0) and their corresponding value definitions. > > This patch makes the TCR_EL1 definitions reusable and uses them for TCR_EL2 > and VTCR_EL2 fields. > > This also fixes a bug where TG0 in {V}TCR_EL2 was treated as 1bit field. > > Cc: Catalin Marinas > Cc: Mark Rutland > Cc: Will Deacon > Cc: Marc Zyngier > Cc: Christoffer Dall > Signed-off-by: Suzuki K Poulose Reviewed-by: Christoffer Dall