From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoffer Dall Subject: Re: [PATCH v4 32/56] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers Date: Wed, 18 May 2016 15:50:22 +0200 Message-ID: <20160518135022.GL3827@cbox> References: <1463392481-26583-1-git-send-email-andre.przywara@arm.com> <1463392481-26583-33-git-send-email-andre.przywara@arm.com> <20160518131449.GI3827@cbox> <573C6EA6.90803@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Marc Zyngier , Eric Auger , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org To: Andre Przywara Return-path: Received: from mail-wm0-f46.google.com ([74.125.82.46]:38062 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932231AbcERNth (ORCPT ); Wed, 18 May 2016 09:49:37 -0400 Received: by mail-wm0-f46.google.com with SMTP id g17so80546719wme.1 for ; Wed, 18 May 2016 06:49:36 -0700 (PDT) Content-Disposition: inline In-Reply-To: <573C6EA6.90803@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, May 18, 2016 at 02:31:18PM +0100, Andre Przywara wrote: > Hi, >=20 > On 18/05/16 14:14, Christoffer Dall wrote: > > On Mon, May 16, 2016 at 10:53:20AM +0100, Andre Przywara wrote: > >> As this register is v2 specific, its implementation lives entirely > >> in vgic-mmio-v2.c. > >> This register allows setting the source mask of an IPI. > >> > >> Signed-off-by: Andre Przywara > >> Reviewed-by: Christoffer Dall > >> --- > >> Changelog RFC..v1: > >> - remove IRQ lock from read handler > >> - update pending bit on setting the first / clearing the last bit > >> - queue virtual IRQ if necessary > >> > >> Changelog v1 .. v2: > >> - adapt to new MMIO framework > >> > >> Changelog v3 .. v4: > >> - specify accessor width > >> > >> virt/kvm/arm/vgic/vgic-mmio-v2.c | 62 +++++++++++++++++++++++++++= +++++++++++-- > >> 1 file changed, 60 insertions(+), 2 deletions(-) > >> > >> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v2.c b/virt/kvm/arm/vgic/= vgic-mmio-v2.c > >> index c884e9b..3925d4c 100644 > >> --- a/virt/kvm/arm/vgic/vgic-mmio-v2.c > >> +++ b/virt/kvm/arm/vgic/vgic-mmio-v2.c > >> @@ -146,6 +146,64 @@ static void vgic_mmio_write_target(struct kvm= _vcpu *vcpu, > >> } > >> } > >> =20 > >> +static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu= , > >> + gpa_t addr, unsigned int len) > >> +{ > >> + u32 intid =3D addr & 0x0f; > >=20 > > is there a reason why we cannot use the magic macro here? >=20 > I wasn't sure about this, because it's not covering all 1024 interrup= ts, > but just SGIs, so it's always fixed to 16 interrupts =E1 8 bits. The > default mask would be too big in this case. > I guess it would work anyway because this region is limited to 16 byt= es > in our description, so we could use this here anyway to make it more > aligned with the other handlers, maybe adding a comment about the > difference? >=20 meh, either way works for me actually, whatever you prefer. Thanks, -Christoffer