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From: Marcelo Tosatti <mtosatti@redhat.com>
To: Alan Jenkins <alan.christopher.jenkins@gmail.com>
Cc: kvm-devel <kvm@vger.kernel.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>
Subject: Re: [PATCH v2] KVM: x86: reset lapic_timer.expired_tscdeadline at SET_LAPIC time
Date: Mon, 20 Jun 2016 22:31:26 -0300	[thread overview]
Message-ID: <20160621013126.GA27650@amt.cnet> (raw)
In-Reply-To: <87bb5b7c-ab8c-7bb4-b01d-f535eb716522@gmail.com>

On Mon, Jun 20, 2016 at 04:20:56PM +0100, Alan Jenkins wrote:
> On 20/06/16 14:05, Marcelo Tosatti wrote:
> >Alan Jenkins reports hang at
> >https://bugzilla.redhat.com/show_bug.cgi?id=1337667,
> >due to guest TSC being set far behind than
> >lapic_timer.expired_tscdeadline, when restoring VM state
> >on top of currently active VM.
> >
> >It is not possible to disable LAPIC timer advancement
> >(by setting lapic_timer.expired_tscdeadline = 0), at
> >guest TSC write
> 
> I like that it acknowledges (though only implicitly) the guest can
> trigger arbitrary lockups of host CPUs.
> 
> >because:
> >
> >* APIC write: expiration = 1000.
> >* LAPIC tsc deadline code sets timer to 1000-30.
> >* Timer fires at 970.
> >* Guest writes TSC=w.
> >
> >Guest fails to VM-entry to process signal to perform
> >"vmload" in userspace.
> >
> >Case 1: w > 970:
> >Guest entry can be performed.
> >
> >Case 2: w < 970:
> >Guest entry should not be performed because "An interrupt is generated
> >when the logical processor’s time-stamp counter equals or exceeds the
> >target value in the IA32_TSC_DEADLINE MSR."
> >
> >In case 2, hardware would not fire an interrupt.
> >
> >To fix the problem, disable timer advancement when
> >userspace sets the LAPIC state. Setting of APIC
> >resets all APIC state, including
> >any pending interrupt.
> >
> >Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
> >Reported-by: Alan Jenkins <alan.christopher.jenkins@gmail.com>
> 
> However I feel this doesn't admit (even implicitly) that host
> software (not necessarily root) can still hard-lockup the CPU. It
> depends on the sequence of operations, and the message doesn't show
> that sequence explicitly. I now understand what the sequence that
> _is_ in the message shows, but it's unfortunately distracting.
> 
> I.e. if you restore the LAPIC first (or omit to do so at all), then
> restore the TSC deadline MSR, then the TSC MSR.
> 
> The patch assumes that the LAPIC is restored after the MSRs so it
> can clear the incorrect value of expired_tscdeadline, right?

Yes.

> I didn't know whether this patch would work until I tested it,
> because I didn't try to nail down the exact sequence QEMU is using.

You are right about the host lockups -- sent another patch to fix that
one.

Thanks for the reports.



  parent reply	other threads:[~2016-06-21  1:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-17 23:41 KVM: x86: reset lapic_timer.expired_tscdeadline at SET_LAPIC time Marcelo Tosatti
2016-06-18 13:43 ` Alan Jenkins
2016-06-20 13:05   ` [PATCH v2] " Marcelo Tosatti
2016-06-20 15:22     ` Alan Jenkins
     [not found]     ` <87bb5b7c-ab8c-7bb4-b01d-f535eb716522@gmail.com>
2016-06-21  1:31       ` Marcelo Tosatti [this message]
2016-06-21  7:50     ` Paolo Bonzini
2016-06-21 11:35       ` Marcelo Tosatti
2016-06-21 11:37         ` Paolo Bonzini
2016-06-20 13:11   ` Marcelo Tosatti
2016-06-20 15:22     ` Alan Jenkins

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