From mboxrd@z Thu Jan 1 00:00:00 1970 From: Radim =?utf-8?B?S3LEjW3DocWZ?= Subject: Re: [PATCH] kvm: nVMX: CPUID.01H:EDX.APIC[bit 9] should mirror IA32_APIC_BASE[11] Date: Tue, 8 Nov 2016 17:33:33 +0100 Message-ID: <20161108163333.GA8352@potion> References: <1478296802-23291-1-git-send-email-jmattson@google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: kvm@vger.kernel.org To: Jim Mattson Return-path: Received: from mx1.redhat.com ([209.132.183.28]:42142 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753902AbcKHQdh (ORCPT ); Tue, 8 Nov 2016 11:33:37 -0500 Content-Disposition: inline In-Reply-To: <1478296802-23291-1-git-send-email-jmattson@google.com> Sender: kvm-owner@vger.kernel.org List-ID: 2016-11-04 15:00-0700, Jim Mattson: > From the Intel SDM, volume 3, section 10.4.3, "Enabling or Disabling the > Local APIC," > > When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent > to an IA-32 processor without an on-chip APIC. The CPUID feature flag > for the APIC (see Section 10.4.2, "Presence of the Local APIC") is > also set to 0. > > Signed-off-by: Jim Mattson > Reviewed-by: Ben Serebrin > Reviewed-by: David Matlack > --- > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > @@ -81,7 +81,10 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu) > best->ecx |= F(OSXSAVE); > } > > + best->edx &= ~F(APIC); This might prevent userspace LAPIC from working. (The bit will always be zero.) > if (apic) { > + if (vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE) > + best->edx |= F(APIC); vcpu->arch.apic_base should be correct regardless of lapic_in_kernel(). Userspace can update CPUID when it changes MSR_IA32_APICBASE_ENABLE, so not handling CPUID update in KVM is fine, but KVM must not touch the CPUID bit in that case. > if (best->ecx & F(TSC_DEADLINE_TIMER)) > apic->lapic_timer.timer_mode_mask = 3 << 17; > else