From mboxrd@z Thu Jan 1 00:00:00 1970 From: Radim =?utf-8?B?S3LEjW3DocWZ?= Subject: Re: [PATCH v3 4/4] KVM: x86: emulate FXSAVE and FXRSTOR Date: Wed, 9 Nov 2016 15:19:37 +0100 Message-ID: <20161109141937.GA32080@potion> References: <20161108195419.4607-1-rkrcmar@redhat.com> <20161108195419.4607-5-rkrcmar@redhat.com> <20161109121200.GA2128@potion> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Bandan Das , Nadav Amit To: Paolo Bonzini Return-path: Content-Disposition: inline In-Reply-To: <20161109121200.GA2128@potion> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org 2016-11-09 13:12+0100, Radim Krčmář: > 2016-11-09 00:25+0100, Paolo Bonzini: >> On 08/11/2016 20:54, Radim Krčmář wrote: >>> +static int em_fxsave(struct x86_emulate_ctxt *ctxt) >>> +{ >>> + struct fxregs_state fx_state; >>> + size_t size = 288; /* up to XMM7 */ >> >> Sorry for noticing this only now; if CR4.OSFXSR is 0, XMM and MXCSR >> should not be saved. > > Intel processors don't save it, but the spec allows saving even when > CR4.OSFXSR is 0: > > If the OSFXSR bit in control register CR4 is not set, the FXSAVE > instruction may not save this register (these registers). > This behavior is implementation dependent. > > I let "implementation dependent" behavior be the one with less code, but > haven't checked AMD spec, which doesn't seem to make it implementation > dependent ... I'll add it. (On intel, OSFXSR gets written with 0 and Nope, Intel always saves and restores MXCSR. I should have access to an AMD machine later today and will implement FXSR to match AMD. > XMM 0-7 isn't modified without OSFXSR, so I'll just assume that AMD > won't break with that.)