From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Xu Subject: Re: [PATCH kvm-unit-tests v5 13/14] pci: add msi support for 32/64bit address Date: Tue, 22 Nov 2016 15:21:37 +0800 Message-ID: <20161122072137.GA4173@pxdev.xzpeter.org> References: <1479248709-10281-1-git-send-email-peterx@redhat.com> <1479248709-10281-14-git-send-email-peterx@redhat.com> <20161121192751.GE30468@agordeev.lab.eng.brq.redhat.com> <20161122045920.GA425@pxdev.xzpeter.org> <20161122070306.GA6720@agordeev.lab.eng.brq.redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Cc: kvm@vger.kernel.org, drjones@redhat.com, jan.kiszka@web.de, rkrcmar@redhat.com, pbonzini@redhat.com To: Alexander Gordeev Return-path: Received: from mx1.redhat.com ([209.132.183.28]:41858 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751736AbcKVHVm (ORCPT ); Tue, 22 Nov 2016 02:21:42 -0500 Content-Disposition: inline In-Reply-To: <20161122070306.GA6720@agordeev.lab.eng.brq.redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On Tue, Nov 22, 2016 at 08:03:06AM +0100, Alexander Gordeev wrote: > On Tue, Nov 22, 2016 at 12:59:20PM +0800, Peter Xu wrote: > > On Mon, Nov 21, 2016 at 08:27:52PM +0100, Alexander Gordeev wrote: > > > > [...] > > > > > > +void pci_cap_walk(struct pci_dev *dev) > > > > +{ > > > > + uint8_t cap_offset; > > > > + uint8_t cap_id; > > > > + > > > > + cap_offset = pci_config_readb(dev->bdf, PCI_CAPABILITY_LIST); > > > > + while (cap_offset) { > > > > + cap_id = pci_config_readb(dev->bdf, cap_offset); > > > > + printf("PCI detected cap 0x%x\n", cap_id); > > > > + if (cap_handlers[cap_id]) > > > > + cap_handlers[cap_id](dev, cap_offset); > > > > + cap_offset = pci_config_readb(dev->bdf, cap_offset + 1); > > > > + } > > > > +} > > > > > > Are you sure the function above is safe without range (sanity) checks? > > > > No. :) But if something goes wrong, I guess that's possibly a QEMU PCI > > bug. I can add some check if you think is necessary, like, make sure > > the loop goes no more than a specific value? > > Yes - I suppose PCI cap. list has a limit. Will do. 0xff should suffice. Thanks, -- peterx