From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kirill A. Shutemov" Subject: Re: [PATCH RFC 0/4] 5-level EPT Date: Thu, 5 Jan 2017 16:26:58 +0300 Message-ID: <20170105132658.GD17319@node.shutemov.name> References: <1483003563-25847-1-git-send-email-liang.z.li@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, kirill.shutemov@linux.intel.com, dave.hansen@linux.intel.com, guangrong.xiao@linux.intel.com, pbonzini@redhat.com, rkrcmar@redhat.com To: Liang Li Return-path: Received: from mail-wj0-f194.google.com ([209.85.210.194]:35751 "EHLO mail-wj0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S970720AbdAENe3 (ORCPT ); Thu, 5 Jan 2017 08:34:29 -0500 Received: by mail-wj0-f194.google.com with SMTP id ey1so88321wjd.2 for ; Thu, 05 Jan 2017 05:34:29 -0800 (PST) Content-Disposition: inline In-Reply-To: <1483003563-25847-1-git-send-email-liang.z.li@intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On Thu, Dec 29, 2016 at 05:25:59PM +0800, Liang Li wrote: > x86-64 is currently limited physical address width to 46 bits, which > can support 64 TiB of memory. Some vendors require to support more for > some use case. Intel plans to extend the physical address width to > 52 bits in some of the future products. > > The current EPT implementation only supports 4 level page table, which > can support maximum 48 bits physical address width, so it's needed to > extend the EPT to 5 level to support 52 bits physical address width. > > This patchset has been tested in the SIMICS environment for 5 level > paging guest, which was patched with Kirill's patchset for enabling > 5 level page table, with both the EPT and shadow page support. I just > covered the booting process, the guest can boot successfully. > > Some parts of this patchset can be improved. Any comments on the design > or the patches would be appreciated. This looks reasonable, assuming my very limited knowledge of the subject. The first patch is actually in my patchset, split across two patches. -- Kirill A. Shutemov