From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoffer Dall Subject: Re: [PATCH 3/5] KVM: arm/arm64: vgic-v2: Do not use Active+Pending state for a HW interrupt Date: Tue, 2 May 2017 22:56:35 +0200 Message-ID: <20170502205635.GA4421@cbox> References: <20170502133041.10980-1-marc.zyngier@arm.com> <20170502133041.10980-4-marc.zyngier@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Christoffer Dall , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org To: Marc Zyngier Return-path: Received: from mail-wm0-f50.google.com ([74.125.82.50]:36875 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750710AbdEBU4h (ORCPT ); Tue, 2 May 2017 16:56:37 -0400 Received: by mail-wm0-f50.google.com with SMTP id m123so34964574wma.0 for ; Tue, 02 May 2017 13:56:37 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20170502133041.10980-4-marc.zyngier@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: On Tue, May 02, 2017 at 02:30:39PM +0100, Marc Zyngier wrote: > When an interrupt is injected with the HW bit set (indicating that > deactivation should be propagated to the physical distributor), > special care must be taken so that we never mark the corresponding > LR with the Active+Pending state (as the pending state is kept in > the physycal distributor). > > Cc: stable@vger.kernel.org > Fixes: 140b086dd197 ("KVM: arm/arm64: vgic-new: Add GICv2 world switch backend") > Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall > --- > virt/kvm/arm/vgic/vgic-v2.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/virt/kvm/arm/vgic/vgic-v2.c b/virt/kvm/arm/vgic/vgic-v2.c > index a65757aab6d3..504b4bd0d651 100644 > --- a/virt/kvm/arm/vgic/vgic-v2.c > +++ b/virt/kvm/arm/vgic/vgic-v2.c > @@ -149,6 +149,13 @@ void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) > if (irq->hw) { > val |= GICH_LR_HW; > val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT; > + /* > + * Never set pending+active on a HW interrupt, as the > + * pending state is kept at the physical distributor > + * level. > + */ > + if (irq->active && irq_is_pending(irq)) > + val &= ~GICH_LR_PENDING_BIT; > } else { > if (irq->config == VGIC_CONFIG_LEVEL) > val |= GICH_LR_EOI; > -- > 2.11.0 >