From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brijesh Singh Subject: [RFC Part1 PATCH v3 07/17] x86/mm: Include SEV for encryption memory attribute changes Date: Mon, 24 Jul 2017 14:07:47 -0500 Message-ID: <20170724190757.11278-8-brijesh.singh@amd.com> References: <20170724190757.11278-1-brijesh.singh@amd.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Borislav Petkov , Andy Lutomirski , Tony Luck , Piotr Luc , Tom Lendacky , Fenghua Yu , Lu Baolu , Reza Arbab , David Howells , Matt Fleming , "Kirill A . Shutemov" , Laura Abbott , Ard Biesheuvel , Andrew Morton , Eric Biederman , Benjamin Herrenschmidt , Paul Mackerras

Received: from mail-sn1nam01on0078.outbound.protection.outlook.com ([104.47.32.78]:14752 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756080AbdGXTJC (ORCPT ); Mon, 24 Jul 2017 15:09:02 -0400 In-Reply-To: <20170724190757.11278-1-brijesh.singh@amd.com> Sender: kvm-owner@vger.kernel.org List-ID: From: Tom Lendacky The current code checks only for sme_active() when determining whether to perform the encryption attribute change. Include sev_active() in this check so that memory attribute changes can occur under SME and SEV. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/mm/pageattr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index dfb7d65..b726b23 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -1781,8 +1781,8 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) unsigned long start; int ret; - /* Nothing to do if the SME is not active */ - if (!sme_active()) + /* Nothing to do if SME and SEV are not active */ + if (!sme_active() && !sev_active()) return 0; /* Should not be working on unaligned addresses */ -- 2.9.4