From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brijesh Singh Subject: [RFC Part2 PATCH v3 07/26] KVM: SVM: Add SEV feature definitions to KVM Date: Mon, 24 Jul 2017 15:02:44 -0500 Message-ID: <20170724200303.12197-8-brijesh.singh@amd.com> References: <20170724200303.12197-1-brijesh.singh@amd.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Thomas Gleixner , Borislav Petkov , Joerg Roedel , "Michael S . Tsirkin" , Paolo Bonzini , =?UTF-8?q?=5C=22Radim=20Kr=C4=8Dm=C3=A1=C5=99=5C=22?= , Tom Lendacky , Brijesh Singh To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Return-path: Received: from mail-by2nam01on0070.outbound.protection.outlook.com ([104.47.34.70]:17488 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751753AbdGXUDx (ORCPT ); Mon, 24 Jul 2017 16:03:53 -0400 In-Reply-To: <20170724200303.12197-1-brijesh.singh@amd.com> Sender: kvm-owner@vger.kernel.org List-ID: From: Tom Lendacky Define the SEV enable bit for the VMCB control structure. The hypervisor will use this bit to enable SEV in the guest. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index a3d9e0b..0be01f9 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -140,6 +140,7 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL #define SVM_NESTED_CTL_NP_ENABLE BIT(0) +#define SVM_NESTED_CTL_SEV_ENABLE BIT(1) struct __attribute__ ((__packed__)) vmcb_seg { u16 selector; -- 2.9.4