* [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY
@ 2017-07-17 13:28 Ladi Prosek
2017-07-24 14:23 ` Radim Krčmář
2017-07-24 17:48 ` Paolo Bonzini
0 siblings, 2 replies; 6+ messages in thread
From: Ladi Prosek @ 2017-07-17 13:28 UTC (permalink / raw)
To: kvm
It has been experimentally confirmed that supporting these two MSRs is one
of the necessary conditions for nested Hyper-V to use the TSC page. Modern
Windows guests are noticeably slower when they fall back to reading
timestamps from the HV_X64_MSR_TIME_REF_COUNT MSR instead of using the TSC
page.
The newly supported MSRs are advertised with the AccessFrequencyRegs
partition privilege flag and CPUID.40000003H:EDX[8] "Support for
determining timer frequencies is available" (both outside of the scope of
this KVM patch).
Hypervisor Top Level Functional Specification version 5.0b does not
explicitly mark these MSRs as partition wide. This is, however, implied by
the way Windows uses them (one read on Hyper-V startup regardless of the
number of VCPUs) as well as our implementation.
Signed-off-by: Ladi Prosek <lprosek@redhat.com>
---
arch/x86/kvm/hyperv.c | 8 ++++++++
arch/x86/kvm/lapic.c | 2 --
arch/x86/kvm/lapic.h | 3 +++
arch/x86/kvm/x86.c | 1 +
4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
index ebae57a..c93ed3a 100644
--- a/arch/x86/kvm/hyperv.c
+++ b/arch/x86/kvm/hyperv.c
@@ -707,6 +707,8 @@ static bool kvm_hv_msr_partition_wide(u32 msr)
case HV_X64_MSR_HYPERCALL:
case HV_X64_MSR_REFERENCE_TSC:
case HV_X64_MSR_TIME_REF_COUNT:
+ case HV_X64_MSR_TSC_FREQUENCY:
+ case HV_X64_MSR_APIC_FREQUENCY:
case HV_X64_MSR_CRASH_CTL:
case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
case HV_X64_MSR_RESET:
@@ -1065,6 +1067,12 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
case HV_X64_MSR_REFERENCE_TSC:
data = hv->hv_tsc_page;
break;
+ case HV_X64_MSR_TSC_FREQUENCY:
+ data = (u64)tsc_khz * 1000;
+ break;
+ case HV_X64_MSR_APIC_FREQUENCY:
+ data = APIC_BUS_FREQUENCY;
+ break;
case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
return kvm_hv_msr_get_crash_data(vcpu,
msr - HV_X64_MSR_CRASH_P0,
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 2819d4c..41110c4 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -54,8 +54,6 @@
#define PRIu64 "u"
#define PRIo64 "o"
-#define APIC_BUS_CYCLE_NS 1
-
/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
#define apic_debug(fmt, arg...)
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 29caa2c..215721e1 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -12,6 +12,9 @@
#define KVM_APIC_SHORT_MASK 0xc0000
#define KVM_APIC_DEST_MASK 0x800
+#define APIC_BUS_CYCLE_NS 1
+#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
+
struct kvm_timer {
struct hrtimer timer;
s64 period; /* unit: ns */
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 6c7266f..94a2eb5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -990,6 +990,7 @@ static u32 emulated_msrs[] = {
MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
+ HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
HV_X64_MSR_RESET,
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY
2017-07-17 13:28 [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY Ladi Prosek
@ 2017-07-24 14:23 ` Radim Krčmář
2017-07-26 9:47 ` Ladi Prosek
2017-07-24 17:48 ` Paolo Bonzini
1 sibling, 1 reply; 6+ messages in thread
From: Radim Krčmář @ 2017-07-24 14:23 UTC (permalink / raw)
To: Ladi Prosek; +Cc: kvm
I missed this patch last week, sorry.
2017-07-17 15:28+0200, Ladi Prosek:
> It has been experimentally confirmed that supporting these two MSRs is one
> of the necessary conditions for nested Hyper-V to use the TSC page. Modern
> Windows guests are noticeably slower when they fall back to reading
> timestamps from the HV_X64_MSR_TIME_REF_COUNT MSR instead of using the TSC
> page.
>
> The newly supported MSRs are advertised with the AccessFrequencyRegs
> partition privilege flag and CPUID.40000003H:EDX[8] "Support for
> determining timer frequencies is available" (both outside of the scope of
> this KVM patch).
Do Windows ignore the AccessFrequencyMsrs (CPUID.40000003H:EAX[11]) bit?
> Hypervisor Top Level Functional Specification version 5.0b does not
> explicitly mark these MSRs as partition wide. This is, however, implied by
> the way Windows uses them (one read on Hyper-V startup regardless of the
> number of VCPUs) as well as our implementation.
>
> Signed-off-by: Ladi Prosek <lprosek@redhat.com>
> ---
> diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
> @@ -1065,6 +1067,12 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
> case HV_X64_MSR_REFERENCE_TSC:
> data = hv->hv_tsc_page;
> break;
> + case HV_X64_MSR_TSC_FREQUENCY:
> + data = (u64)tsc_khz * 1000;
> + break;
This should be based on vcpu->arch.virtual_tsc_khz, because KVM can use
guest TSC scaling,
thanks.
> + case HV_X64_MSR_APIC_FREQUENCY:
> + data = APIC_BUS_FREQUENCY;
> + break;
> case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
> return kvm_hv_msr_get_crash_data(vcpu,
> msr - HV_X64_MSR_CRASH_P0,
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY
2017-07-17 13:28 [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY Ladi Prosek
2017-07-24 14:23 ` Radim Krčmář
@ 2017-07-24 17:48 ` Paolo Bonzini
2017-07-26 9:51 ` Ladi Prosek
1 sibling, 1 reply; 6+ messages in thread
From: Paolo Bonzini @ 2017-07-24 17:48 UTC (permalink / raw)
To: Ladi Prosek, kvm
On 17/07/2017 15:28, Ladi Prosek wrote:
> It has been experimentally confirmed that supporting these two MSRs is one
> of the necessary conditions for nested Hyper-V to use the TSC page. Modern
> Windows guests are noticeably slower when they fall back to reading
> timestamps from the HV_X64_MSR_TIME_REF_COUNT MSR instead of using the TSC
> page.
>
> The newly supported MSRs are advertised with the AccessFrequencyRegs
> partition privilege flag and CPUID.40000003H:EDX[8] "Support for
> determining timer frequencies is available" (both outside of the scope of
> this KVM patch).
>
> Hypervisor Top Level Functional Specification version 5.0b does not
> explicitly mark these MSRs as partition wide. This is, however, implied by
> the way Windows uses them (one read on Hyper-V startup regardless of the
> number of VCPUs) as well as our implementation.
>
> Signed-off-by: Ladi Prosek <lprosek@redhat.com>
No opposition to adding these registers, but QEMU must only present them
if the TSC frequency is stable across migration and known, that is
/* TSC clock must be stable and known for this feature. */
&& ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
|| env->user_tsc_khz != 0)
&& env->tsc_khz != 0
(A similar condition is already used for cpu->vmware_cpuid_freq).
Paolo
> ---
> arch/x86/kvm/hyperv.c | 8 ++++++++
> arch/x86/kvm/lapic.c | 2 --
> arch/x86/kvm/lapic.h | 3 +++
> arch/x86/kvm/x86.c | 1 +
> 4 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
> index ebae57a..c93ed3a 100644
> --- a/arch/x86/kvm/hyperv.c
> +++ b/arch/x86/kvm/hyperv.c
> @@ -707,6 +707,8 @@ static bool kvm_hv_msr_partition_wide(u32 msr)
> case HV_X64_MSR_HYPERCALL:
> case HV_X64_MSR_REFERENCE_TSC:
> case HV_X64_MSR_TIME_REF_COUNT:
> + case HV_X64_MSR_TSC_FREQUENCY:
> + case HV_X64_MSR_APIC_FREQUENCY:
> case HV_X64_MSR_CRASH_CTL:
> case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
> case HV_X64_MSR_RESET:
> @@ -1065,6 +1067,12 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
> case HV_X64_MSR_REFERENCE_TSC:
> data = hv->hv_tsc_page;
> break;
> + case HV_X64_MSR_TSC_FREQUENCY:
> + data = (u64)tsc_khz * 1000;
> + break;
> + case HV_X64_MSR_APIC_FREQUENCY:
> + data = APIC_BUS_FREQUENCY;
> + break;
> case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
> return kvm_hv_msr_get_crash_data(vcpu,
> msr - HV_X64_MSR_CRASH_P0,
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 2819d4c..41110c4 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -54,8 +54,6 @@
> #define PRIu64 "u"
> #define PRIo64 "o"
>
> -#define APIC_BUS_CYCLE_NS 1
> -
> /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
> #define apic_debug(fmt, arg...)
>
> diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
> index 29caa2c..215721e1 100644
> --- a/arch/x86/kvm/lapic.h
> +++ b/arch/x86/kvm/lapic.h
> @@ -12,6 +12,9 @@
> #define KVM_APIC_SHORT_MASK 0xc0000
> #define KVM_APIC_DEST_MASK 0x800
>
> +#define APIC_BUS_CYCLE_NS 1
> +#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
> +
> struct kvm_timer {
> struct hrtimer timer;
> s64 period; /* unit: ns */
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 6c7266f..94a2eb5 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -990,6 +990,7 @@ static u32 emulated_msrs[] = {
> MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
> HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
> HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
> + HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
> HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
> HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
> HV_X64_MSR_RESET,
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY
2017-07-24 14:23 ` Radim Krčmář
@ 2017-07-26 9:47 ` Ladi Prosek
2017-07-26 12:45 ` Radim Krčmář
0 siblings, 1 reply; 6+ messages in thread
From: Ladi Prosek @ 2017-07-26 9:47 UTC (permalink / raw)
To: Radim Krčmář; +Cc: KVM list
On Mon, Jul 24, 2017 at 4:23 PM, Radim Krčmář <rkrcmar@redhat.com> wrote:
> I missed this patch last week, sorry.
>
> 2017-07-17 15:28+0200, Ladi Prosek:
>> It has been experimentally confirmed that supporting these two MSRs is one
>> of the necessary conditions for nested Hyper-V to use the TSC page. Modern
>> Windows guests are noticeably slower when they fall back to reading
>> timestamps from the HV_X64_MSR_TIME_REF_COUNT MSR instead of using the TSC
>> page.
>>
>> The newly supported MSRs are advertised with the AccessFrequencyRegs
>> partition privilege flag and CPUID.40000003H:EDX[8] "Support for
>> determining timer frequencies is available" (both outside of the scope of
>> this KVM patch).
>
> Do Windows ignore the AccessFrequencyMsrs (CPUID.40000003H:EAX[11]) bit?
No, Windows won't read the MSRs without CPUID.40000003H:EAX[11]. The
other bit (CPUID.40000003H:EDX[8]) appears to be ignored, or at least
I couldn't find any difference in behavior.
I wonder why you're asking, i.e. what is it that I'm misunderstanding :)
>> Hypervisor Top Level Functional Specification version 5.0b does not
>> explicitly mark these MSRs as partition wide. This is, however, implied by
>> the way Windows uses them (one read on Hyper-V startup regardless of the
>> number of VCPUs) as well as our implementation.
>>
>> Signed-off-by: Ladi Prosek <lprosek@redhat.com>
>> ---
>> diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
>> @@ -1065,6 +1067,12 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
>> case HV_X64_MSR_REFERENCE_TSC:
>> data = hv->hv_tsc_page;
>> break;
>> + case HV_X64_MSR_TSC_FREQUENCY:
>> + data = (u64)tsc_khz * 1000;
>> + break;
>
> This should be based on vcpu->arch.virtual_tsc_khz, because KVM can use
> guest TSC scaling,
Ah, of course. Thanks!
> thanks.
>
>> + case HV_X64_MSR_APIC_FREQUENCY:
>> + data = APIC_BUS_FREQUENCY;
>> + break;
>> case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
>> return kvm_hv_msr_get_crash_data(vcpu,
>> msr - HV_X64_MSR_CRASH_P0,
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY
2017-07-24 17:48 ` Paolo Bonzini
@ 2017-07-26 9:51 ` Ladi Prosek
0 siblings, 0 replies; 6+ messages in thread
From: Ladi Prosek @ 2017-07-26 9:51 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: KVM list
On Mon, Jul 24, 2017 at 7:48 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> On 17/07/2017 15:28, Ladi Prosek wrote:
>> It has been experimentally confirmed that supporting these two MSRs is one
>> of the necessary conditions for nested Hyper-V to use the TSC page. Modern
>> Windows guests are noticeably slower when they fall back to reading
>> timestamps from the HV_X64_MSR_TIME_REF_COUNT MSR instead of using the TSC
>> page.
>>
>> The newly supported MSRs are advertised with the AccessFrequencyRegs
>> partition privilege flag and CPUID.40000003H:EDX[8] "Support for
>> determining timer frequencies is available" (both outside of the scope of
>> this KVM patch).
>>
>> Hypervisor Top Level Functional Specification version 5.0b does not
>> explicitly mark these MSRs as partition wide. This is, however, implied by
>> the way Windows uses them (one read on Hyper-V startup regardless of the
>> number of VCPUs) as well as our implementation.
>>
>> Signed-off-by: Ladi Prosek <lprosek@redhat.com>
>
> No opposition to adding these registers, but QEMU must only present them
> if the TSC frequency is stable across migration and known, that is
>
> /* TSC clock must be stable and known for this feature. */
> && ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
> || env->user_tsc_khz != 0)
> && env->tsc_khz != 0
>
> (A similar condition is already used for cpu->vmware_cpuid_freq).
Will do! Hyper-V won't initialize L2's TSC pages without
CPUID_APM_INVTSC anyway.
> Paolo
>
>> ---
>> arch/x86/kvm/hyperv.c | 8 ++++++++
>> arch/x86/kvm/lapic.c | 2 --
>> arch/x86/kvm/lapic.h | 3 +++
>> arch/x86/kvm/x86.c | 1 +
>> 4 files changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
>> index ebae57a..c93ed3a 100644
>> --- a/arch/x86/kvm/hyperv.c
>> +++ b/arch/x86/kvm/hyperv.c
>> @@ -707,6 +707,8 @@ static bool kvm_hv_msr_partition_wide(u32 msr)
>> case HV_X64_MSR_HYPERCALL:
>> case HV_X64_MSR_REFERENCE_TSC:
>> case HV_X64_MSR_TIME_REF_COUNT:
>> + case HV_X64_MSR_TSC_FREQUENCY:
>> + case HV_X64_MSR_APIC_FREQUENCY:
>> case HV_X64_MSR_CRASH_CTL:
>> case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
>> case HV_X64_MSR_RESET:
>> @@ -1065,6 +1067,12 @@ static int kvm_hv_get_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
>> case HV_X64_MSR_REFERENCE_TSC:
>> data = hv->hv_tsc_page;
>> break;
>> + case HV_X64_MSR_TSC_FREQUENCY:
>> + data = (u64)tsc_khz * 1000;
>> + break;
>> + case HV_X64_MSR_APIC_FREQUENCY:
>> + data = APIC_BUS_FREQUENCY;
>> + break;
>> case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
>> return kvm_hv_msr_get_crash_data(vcpu,
>> msr - HV_X64_MSR_CRASH_P0,
>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>> index 2819d4c..41110c4 100644
>> --- a/arch/x86/kvm/lapic.c
>> +++ b/arch/x86/kvm/lapic.c
>> @@ -54,8 +54,6 @@
>> #define PRIu64 "u"
>> #define PRIo64 "o"
>>
>> -#define APIC_BUS_CYCLE_NS 1
>> -
>> /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
>> #define apic_debug(fmt, arg...)
>>
>> diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
>> index 29caa2c..215721e1 100644
>> --- a/arch/x86/kvm/lapic.h
>> +++ b/arch/x86/kvm/lapic.h
>> @@ -12,6 +12,9 @@
>> #define KVM_APIC_SHORT_MASK 0xc0000
>> #define KVM_APIC_DEST_MASK 0x800
>>
>> +#define APIC_BUS_CYCLE_NS 1
>> +#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
>> +
>> struct kvm_timer {
>> struct hrtimer timer;
>> s64 period; /* unit: ns */
>> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
>> index 6c7266f..94a2eb5 100644
>> --- a/arch/x86/kvm/x86.c
>> +++ b/arch/x86/kvm/x86.c
>> @@ -990,6 +990,7 @@ static u32 emulated_msrs[] = {
>> MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
>> HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
>> HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
>> + HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
>> HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
>> HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
>> HV_X64_MSR_RESET,
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY
2017-07-26 9:47 ` Ladi Prosek
@ 2017-07-26 12:45 ` Radim Krčmář
0 siblings, 0 replies; 6+ messages in thread
From: Radim Krčmář @ 2017-07-26 12:45 UTC (permalink / raw)
To: Ladi Prosek; +Cc: KVM list
2017-07-26 11:47+0200, Ladi Prosek:
> On Mon, Jul 24, 2017 at 4:23 PM, Radim Krčmář <rkrcmar@redhat.com> wrote:
> > 2017-07-17 15:28+0200, Ladi Prosek:
> >> The newly supported MSRs are advertised with the AccessFrequencyRegs
> >> partition privilege flag and CPUID.40000003H:EDX[8] "Support for
> >> determining timer frequencies is available" (both outside of the scope of
> >> this KVM patch).
> >
> > Do Windows ignore the AccessFrequencyMsrs (CPUID.40000003H:EAX[11]) bit?
>
> No, Windows won't read the MSRs without CPUID.40000003H:EAX[11]. The
> other bit (CPUID.40000003H:EDX[8]) appears to be ignored, or at least
> I couldn't find any difference in behavior.
Looking more into it, we are emulating non-root partitions, where
CPUID.40000003H:EDX[8] would probably be clear and then the check Linux
has in ms_hyperv_init_platform() could be wrong. I am not sure what
FrequencyMsrsAvailable is for, though -- to allow AccessFrequencyMsrs in
non-root even if root has AccessFrequencyMsrs disabled?
> I wonder why you're asking, i.e. what is it that I'm misunderstanding :)
I was just curious why you didn't mention both in the same way
(CamelCase name or CPUID bit) and the best explanation was that you
didn't need to care about one, because Windows worked without it. :)
I think you got it all right.
Thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-07-26 12:46 UTC | newest]
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2017-07-17 13:28 [PATCH] KVM: hyperv: support HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY Ladi Prosek
2017-07-24 14:23 ` Radim Krčmář
2017-07-26 9:47 ` Ladi Prosek
2017-07-26 12:45 ` Radim Krčmář
2017-07-24 17:48 ` Paolo Bonzini
2017-07-26 9:51 ` Ladi Prosek
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