From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v3 3/9] arm64: KVM: Add invalidate_icache_range helper Date: Mon, 23 Oct 2017 17:19:14 +0100 Message-ID: <20171023161914.GA6222@arm.com> References: <20171023161122.15291-1-marc.zyngier@arm.com> <20171023161122.15291-4-marc.zyngier@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Christoffer Dall , Catalin Marinas , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu To: Marc Zyngier Return-path: Received: from foss.arm.com ([217.140.101.70]:40944 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdJWQTP (ORCPT ); Mon, 23 Oct 2017 12:19:15 -0400 Content-Disposition: inline In-Reply-To: <20171023161122.15291-4-marc.zyngier@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: On Mon, Oct 23, 2017 at 05:11:16PM +0100, Marc Zyngier wrote: > We currently tightly couple dcache clean with icache invalidation, > but KVM could do without the initial flush to PoU, as we've > already flushed things to PoC. > > Let's introduce invalidate_icache_range which is limited to > invalidating the icache from the linear mapping (and thus > has none of the userspace fault handling complexity), and > wire it in KVM instead of flush_icache_range. > > Reviewed-by: Christoffer Dall > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/assembler.h | 21 +++++++++++++++++++++ > arch/arm64/include/asm/cacheflush.h | 7 +++++++ > arch/arm64/include/asm/kvm_mmu.h | 4 ++-- > arch/arm64/mm/cache.S | 32 ++++++++++++++++++++++---------- > 4 files changed, 52 insertions(+), 12 deletions(-) Acked-by: Will Deacon Thanks for respinning this. Will