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From: Andi Kleen <ak@linux.intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: "Wanpeng Li" <kernellwp@gmail.com>,
	LKML <linux-kernel@vger.kernel.org>,
	"kvm list" <kvm@vger.kernel.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>,
	"Wanpeng Li" <wanpeng.li@hotmail.com>
Subject: Re: [PATCH] KVM: VMX: Cache IA32_DEBUGCTL in memory
Date: Wed, 29 Nov 2017 12:56:24 -0800	[thread overview]
Message-ID: <20171129205624.GD3070@tassilo.jf.intel.com> (raw)
In-Reply-To: <CALMp9eSmqa8Wgvcwa=58CvBndfKQ6N_Uf8HTpMPe8WC_gM-iGA@mail.gmail.com>

On Wed, Nov 29, 2017 at 11:05:46AM -0800, Jim Mattson wrote:
> An alternative is to give the L1 guest read permission for this MSR in
> the MSR permission bitmaps. It's still going to be ~80 cycles, but
> that's better than the cost of a VM-exit/VM-entry round-trip.

It's a useful optimization, 80 cycles is 80 cycles.

The cache invalidation could likely be really simple, like:
have a global counter
always check the counter before and after and don't use the cache
if they don't match.
change KDB etc. to increase the counter.

-Andi

  reply	other threads:[~2017-11-29 20:56 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-29  6:07 [PATCH] KVM: VMX: Cache IA32_DEBUGCTL in memory Wanpeng Li
2017-11-29  8:48 ` Paolo Bonzini
2017-11-29  8:51   ` Wanpeng Li
2017-11-29  9:13     ` Paolo Bonzini
2017-11-29  9:20       ` Wanpeng Li
2017-11-29 18:20 ` Andi Kleen
2017-11-29 19:05   ` Jim Mattson
2017-11-29 20:56     ` Andi Kleen [this message]
2017-11-29 22:26   ` Paolo Bonzini
2017-11-29 22:45     ` Andi Kleen

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