From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Jones Subject: [PATCH kvm-unit-tests v2 04/12] arm/arm64: flush page table cache when installing entries Date: Wed, 17 Jan 2018 11:39:57 +0100 Message-ID: <20180117104005.29211-5-drjones@redhat.com> References: <20180117104005.29211-1-drjones@redhat.com> Cc: pbonzini@redhat.com, rkrcmar@redhat.com, cdall@linaro.org, david@redhat.com, lvivier@redhat.com, thuth@redhat.com To: kvm@vger.kernel.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:44351 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752640AbeAQKkY (ORCPT ); Wed, 17 Jan 2018 05:40:24 -0500 In-Reply-To: <20180117104005.29211-1-drjones@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: This fixes the use of non-identity mapped page table entries for arm32 and AArch32 unit tests. Signed-off-by: Andrew Jones --- lib/arm/asm/mmu.h | 5 +++++ lib/arm/mmu.c | 17 +++++++++++++++-- lib/arm64/asm/mmu.h | 5 +++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/lib/arm/asm/mmu.h b/lib/arm/asm/mmu.h index a31e19cd6652..915c2b07dead 100644 --- a/lib/arm/asm/mmu.h +++ b/lib/arm/asm/mmu.h @@ -37,6 +37,11 @@ static inline void flush_tlb_page(unsigned long vaddr) isb(); } +static inline void flush_dcache_addr(unsigned long vaddr) +{ + asm volatile("mcr p15, 0, %0, c7, c14, 1" :: "r" (vaddr)); +} + #include #endif /* __ASMARM_MMU_H_ */ diff --git a/lib/arm/mmu.c b/lib/arm/mmu.c index 9da3be38b339..548ec88277bc 100644 --- a/lib/arm/mmu.c +++ b/lib/arm/mmu.c @@ -73,6 +73,17 @@ void mmu_disable(void) asm_mmu_disable(); } +static void flush_entry(pgd_t *pgtable, uintptr_t vaddr) +{ + pgd_t *pgd = pgd_offset(pgtable, vaddr); + pmd_t *pmd = pmd_offset(pgd, vaddr); + + flush_dcache_addr((ulong)pgd); + flush_dcache_addr((ulong)pmd); + flush_dcache_addr((ulong)pte_offset(pmd, vaddr)); + flush_tlb_page(vaddr); +} + static pteval_t *get_pte(pgd_t *pgtable, uintptr_t vaddr) { pgd_t *pgd = pgd_offset(pgtable, vaddr); @@ -85,8 +96,9 @@ static pteval_t *get_pte(pgd_t *pgtable, uintptr_t vaddr) static pteval_t *install_pte(pgd_t *pgtable, uintptr_t vaddr, pteval_t pte) { pteval_t *p_pte = get_pte(pgtable, vaddr); + *p_pte = pte; - flush_tlb_page(vaddr); + flush_entry(pgtable, vaddr); return p_pte; } @@ -136,8 +148,9 @@ void mmu_set_range_sect(pgd_t *pgtable, uintptr_t virt_offset, pgd_val(*pgd) = paddr; pgd_val(*pgd) |= PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S; pgd_val(*pgd) |= pgprot_val(prot); + flush_dcache_addr((ulong)pgd); + flush_tlb_page(vaddr); } - flush_tlb_all(); } void *setup_mmu(phys_addr_t phys_end) diff --git a/lib/arm64/asm/mmu.h b/lib/arm64/asm/mmu.h index 9df99cc8871e..fa554b0c20ae 100644 --- a/lib/arm64/asm/mmu.h +++ b/lib/arm64/asm/mmu.h @@ -26,6 +26,11 @@ static inline void flush_tlb_page(unsigned long vaddr) dsb(ish); } +static inline void flush_dcache_addr(unsigned long vaddr) +{ + asm volatile("dc civac, %0" :: "r" (vaddr)); +} + #include #endif /* __ASMARM64_MMU_H_ */ -- 2.13.6