From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eduardo Habkost Subject: Re: [RFC,05/10] x86/speculation: Add basic IBRS support infrastructure Date: Mon, 29 Jan 2018 19:44:21 -0200 Message-ID: <20180129214421.GW25150@localhost.localdomain> References: <1516476182-5153-6-git-send-email-karahmed@amazon.de> <20180129201404.GA1588@localhost.localdomain> <1517257022.18619.30.camel@infradead.org> <20180129204256.GV25150@localhost.localdomain> <31415b7f-9c76-c102-86cd-6bf4e23e3aee@linux.intel.com> <1517259759.18619.38.camel@infradead.org> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Cc: Arjan van de Ven , KarimAllah Ahmed , linux-kernel@vger.kernel.org, Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Linus Torvalds , Masami Hiramatsu Return-path: Received: from mx1.redhat.com ([209.132.183.28]:52380 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751698AbeA2VoY (ORCPT ); Mon, 29 Jan 2018 16:44:24 -0500 Content-Disposition: inline In-Reply-To: <1517259759.18619.38.camel@infradead.org> Sender: kvm-owner@vger.kernel.org List-ID: On Mon, Jan 29, 2018 at 09:02:39PM +0000, David Woodhouse wrote: > > > On Mon, 2018-01-29 at 12:44 -0800, Arjan van de Ven wrote: > > On 1/29/2018 12:42 PM, Eduardo Habkost wrote: > > > > > > The question is how the hypervisor could tell that to the guest. > > > If Intel doesn't give us a CPUID bit that can be used to tell > > > that retpolines are enough, maybe we should use a hypervisor > > > CPUID bit for that? > > > > the objective is to have retpoline be safe everywhere and never use IBRS > > (Linus was also pretty clear about that) so I'm confused by your question > > The question is about all the additional RSB-frobbing and call depth > counting and other bits that don't really even exist for Skylake yet in > a coherent form. > > If a guest doesn't have those, because it's running some future kernel > where they *are* implemented but not enabled because at *boot* time it > discovered it wasn't on Skylake, the question is what happens if that > guest is subsequently migrated to a Skylake-class machine. > > To which the answer is obviously "oops, sucks to be you". So yes, > *maybe* we want a way to advertise "you might be migrated to Skylake" > if you're booted on a pre-SKL box in a migration pool where such is > possible.  > > That question is a reasonable one, and the answer possibly the same, > regardless of whether the plan for Skylake is to use IBRS, or all the > hypothetical other extra stuff. Maybe a generic "family/model/stepping/microcode really matches the CPU you are running on" bit would be useful. The bit could be enabled only on host-passthrough (aka "-cpu host") mode. If we really want to be able to migrate to host with different CPU models (except Skylake), we could add a more specific "we promise the host CPU is never going to be Skylake" bit. Now, if the hypervisor is not providing any of those bits, I would advise against trusting family/model/stepping/microcode under a hypervisor. Using a pre-defined CPU model (that doesn't necessarily match the host) is very common when using KVM VM management stacks. -- Eduardo