From mboxrd@z Thu Jan 1 00:00:00 1970 From: Konrad Rzeszutek Wilk Subject: Re: [PATCH v6 3/5] KVM: VMX: Emulate MSR_IA32_ARCH_CAPABILITIES Date: Fri, 2 Feb 2018 12:51:00 -0500 Message-ID: <20180202175100.GS28192@char.us.oracle.com> References: <1517522386-18410-1-git-send-email-karahmed@amazon.de> <1517522386-18410-4-git-send-email-karahmed@amazon.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, Asit Mallick , Dave Hansen , Arjan Van De Ven , Tim Chen , Linus Torvalds , Andrea Arcangeli , Andi Kleen , Thomas Gleixner , Dan Williams , Jun Nakajima , Andy Lutomirski , Greg KH , Paolo Bonzini , Ashok Raj , David Woodhouse To: KarimAllah Ahmed Return-path: Received: from userp2120.oracle.com ([156.151.31.85]:50932 "EHLO userp2120.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753038AbeBBRvW (ORCPT ); Fri, 2 Feb 2018 12:51:22 -0500 Content-Disposition: inline In-Reply-To: <1517522386-18410-4-git-send-email-karahmed@amazon.de> Sender: kvm-owner@vger.kernel.org List-ID: On Thu, Feb 01, 2018 at 10:59:44PM +0100, KarimAllah Ahmed wrote: > Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO > (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the > contents will come directly from the hardware, but user-space can still > override it. > > [dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional] > > Cc: Asit Mallick > Cc: Dave Hansen > Cc: Arjan Van De Ven > Cc: Tim Chen > Cc: Linus Torvalds > Cc: Andrea Arcangeli > Cc: Andi Kleen > Cc: Thomas Gleixner > Cc: Dan Williams > Cc: Jun Nakajima > Cc: Andy Lutomirski > Cc: Greg KH > Cc: Paolo Bonzini > Cc: Ashok Raj > Reviewed-by: Paolo Bonzini Reviewed-by: Konrad Rzeszutek Wilk