From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eduardo Habkost Subject: Re: [PATCH v7 3/9] i386: Initialize cache information for EPYC family processors Date: Mon, 7 May 2018 17:22:56 -0300 Message-ID: <20180507202256.GG13350@localhost.localdomain> References: <1524760009-24710-1-git-send-email-babu.moger@amd.com> <1524760009-24710-4-git-send-email-babu.moger@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: geoff@hostfission.com, kvm@vger.kernel.org, mst@redhat.com, kash@tripleback.net, mtosatti@redhat.com, qemu-devel@nongnu.org, marcel@redhat.com, pbonzini@redhat.com, rth@twiddle.net To: Babu Moger Return-path: Content-Disposition: inline In-Reply-To: <1524760009-24710-4-git-send-email-babu.moger@amd.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel2=m.gmane.org@nongnu.org Sender: "Qemu-devel" List-Id: kvm.vger.kernel.org On Thu, Apr 26, 2018 at 11:26:43AM -0500, Babu Moger wrote: > Initialize pre-determined cache information for EPYC processors. > > Signed-off-by: Babu Moger > Tested-by: Geoffrey McRae Assuming that the cache information below was validated by people from AMD, patch looks good to me. > --- > target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index a518a0f..5d88363 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -2302,6 +2302,54 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "AMD EPYC Processor", > + .cache_info.valid = 1, > + .cache_info.l1d_cache = { > + .type = DCACHE, > + .level = 1, > + .size = 32 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 64, > + .lines_per_tag = 1, > + .self_init = 1, > + .no_invd_sharing = true, > + }, > + .cache_info.l1i_cache = { > + .type = ICACHE, > + .level = 1, > + .size = 64 * KiB, > + .line_size = 64, > + .associativity = 4, > + .partitions = 1, > + .sets = 256, > + .lines_per_tag = 1, > + .self_init = 1, > + .no_invd_sharing = true, > + }, > + .cache_info.l2_cache = { > + .type = UNIFIED_CACHE, > + .level = 2, > + .size = 512 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 1024, > + .lines_per_tag = 1, > + }, > + .cache_info.l3_cache = { > + .type = UNIFIED_CACHE, > + .level = 3, > + .size = 8 * MiB, > + .line_size = 64, > + .associativity = 16, > + .partitions = 1, > + .sets = 8192, > + .lines_per_tag = 1, > + .self_init = true, > + .inclusive = true, > + .complex_indexing = true, > + }, > }, > { > .name = "EPYC-IBPB", > @@ -2348,6 +2396,54 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_6_EAX_ARAT, > .xlevel = 0x8000000A, > .model_id = "AMD EPYC Processor (with IBPB)", > + .cache_info.valid = 1, > + .cache_info.l1d_cache = { > + .type = DCACHE, > + .level = 1, > + .size = 32 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 64, > + .lines_per_tag = 1, > + .self_init = 1, > + .no_invd_sharing = true, > + }, > + .cache_info.l1i_cache = { > + .type = ICACHE, > + .level = 1, > + .size = 64 * KiB, > + .line_size = 64, > + .associativity = 4, > + .partitions = 1, > + .sets = 256, > + .lines_per_tag = 1, > + .self_init = 1, > + .no_invd_sharing = true, > + }, > + .cache_info.l2_cache = { > + .type = UNIFIED_CACHE, > + .level = 2, > + .size = 512 * KiB, > + .line_size = 64, > + .associativity = 8, > + .partitions = 1, > + .sets = 1024, > + .lines_per_tag = 1, > + }, > + .cache_info.l3_cache = { > + .type = UNIFIED_CACHE, > + .level = 3, > + .size = 8 * MiB, > + .line_size = 64, > + .associativity = 16, > + .partitions = 1, > + .sets = 8192, > + .lines_per_tag = 1, > + .self_init = true, > + .inclusive = true, > + .complex_indexing = true, > + }, > }, > }; > > -- > 2.7.4 > > -- Eduardo