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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	x86@kernel.org, tglx@linutronix.de, andrew.cooper3@citrix.com
Subject: Re: [PATCH v1] AMD SSB bits.
Date: Tue, 5 Jun 2018 16:56:00 -0400	[thread overview]
Message-ID: <20180605205600.GR5867@char.us.oracle.com> (raw)
In-Reply-To: <f1281c9e-7efd-cf87-c093-b86a9014aa24@amd.com>

On Tue, Jun 05, 2018 at 08:23:13AM -0500, Tom Lendacky wrote:
> On 6/1/2018 9:59 AM, Konrad Rzeszutek Wilk wrote:
> > Hi,
> > 
> > I was reading the AMD whitepaper on SSBD and noticed that they have added
> > two new bits in the 8000_0008 CPUID. EBX:
> >  1) Bit[26] - similar to Intel's SSB_NO not needed anymore.
> >  2) Bit[24] - use SPEC_CTRL MSR (0x48) instead of VIRT SPEC_CTRL MSR
> >     (0xC001_011f).
> > 
> > See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> > (A copy of this document is available at
> >     https://bugzilla.kernel.org/show_bug.cgi?id=199889)
> > 
> > Being that I don't have the hardware (not even sure if AMD has developed it yet)
> > I ended up cobbling up a DEBUG patch, the last one - which is well, debug
> > (see below).
> 
> So I'm not sure what is debug and what isn't, so I'm just commenting as if
> they weren't debug.  If this patch is just for debug, then you can
> probably ignore.

It is just for debugging.

      reply	other threads:[~2018-06-05 20:56 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-01 14:59 [PATCH v1] AMD SSB bits Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 1/3] x86/bugs: Add AMD's variant of SSB_NO Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 2/3] x86/bugs: Add AMD's SPEC_CTRL MSR usage Konrad Rzeszutek Wilk
2018-06-02  1:04   ` Tom Lendacky
2018-06-04 20:20     ` Konrad Rzeszutek Wilk
2018-06-04 20:43       ` Tom Lendacky
2018-06-04 20:54         ` Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 3/3] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features Konrad Rzeszutek Wilk
2018-06-08 21:30   ` Tom Lendacky
2018-06-11 14:01     ` Konrad Rzeszutek Wilk
2018-06-12 14:38       ` Tom Lendacky
2018-06-15 18:57         ` Thomas Gleixner
2018-06-15 19:38           ` Konrad Rzeszutek Wilk
2018-06-01 15:38 ` [PATCH QEMU] Patches for new AMD CPU bits Konrad Rzeszutek Wilk
2018-06-01 15:38   ` [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit Konrad Rzeszutek Wilk
2018-06-04  8:54     ` Daniel P. Berrangé
2018-06-04 20:20       ` Konrad Rzeszutek Wilk
2018-06-04 20:07     ` Eduardo Habkost
2018-06-04 20:22       ` Konrad Rzeszutek Wilk
2018-06-04 21:15         ` Eduardo Habkost
2018-06-05 21:40           ` Konrad Rzeszutek Wilk
2018-06-13 10:19         ` Daniel P. Berrangé
2018-06-13 16:09           ` Konrad Rzeszutek Wilk
2018-06-13 16:21             ` Daniel P. Berrangé
2018-06-13 16:34               ` Konrad Rzeszutek Wilk
2018-06-13 16:39                 ` Daniel P. Berrangé
2018-06-13 16:56                   ` Eduardo Habkost
2018-06-05 13:31       ` Tom Lendacky
2018-06-05 14:04         ` Daniel P. Berrangé
2018-06-06 14:20         ` Daniel P. Berrangé
2018-06-08 21:22           ` Tom Lendacky
2018-06-01 15:38   ` [PATCH 2/2] i386: Define AMD's no SSB mitigation needed Konrad Rzeszutek Wilk
2018-06-13 21:38   ` [PATCH QEMU] Patches for new AMD CPU bits Eduardo Habkost
2018-06-05 13:23 ` [PATCH v1] AMD SSB bits Tom Lendacky
2018-06-05 20:56   ` Konrad Rzeszutek Wilk [this message]

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