From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eduardo Habkost Subject: Re: [PATCH QEMU] Patches for new AMD CPU bits. Date: Wed, 13 Jun 2018 18:38:58 -0300 Message-ID: <20180613213858.GI24764@localhost.localdomain> References: <20180601145921.9500-1-konrad.wilk@oracle.com> <20180601153809.15259-1-konrad.wilk@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org, rth@twiddle.net To: Konrad Rzeszutek Wilk Return-path: Content-Disposition: inline In-Reply-To: <20180601153809.15259-1-konrad.wilk@oracle.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel2=m.gmane.org@nongnu.org Sender: "Qemu-devel" List-Id: kvm.vger.kernel.org On Fri, Jun 01, 2018 at 11:38:07AM -0400, Konrad Rzeszutek Wilk wrote: > Hi! > > > I was reading the AMD whitepaper on SSBD and noticed that they have added > two new bits in the 8000_0008 CPUID. EBX: > 1) Bit[26] - similar to Intel's SSB_NO not needed anymore. > 2) Bit[24] - use SPEC_CTRL MSR (0x48) instead of VIRT SPEC_CTRL MSR > (0xC001_011f). > > See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf > A copy of this document is available at > https://bugzilla.kernel.org/show_bug.cgi?id=199889 > > These two patches along with the kernel ones allow us to expose those > two bits to the guest. Queued on x86-next, thanks! -- Eduardo