From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Michael S. Tsirkin" Subject: Re: [PATCH V4 4/4] target-i386: add i440fx 0xcf8 portascoalesced_pio Date: Thu, 30 Aug 2018 23:39:44 -0400 Message-ID: <20180830233835-mutt-send-email-mst@kernel.org> References: <201808272317499067164@zte.com.cn> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: zhong.weidong@zte.com.cn, ehabkost@redhat.com, kvm@vger.kernel.org, rkrcmar@redhat.com, qemu-devel@nongnu.org, liran.alon@oracle.com, pbonzini@redhat.com To: peng.hao2@zte.com.cn Return-path: Content-Disposition: inline In-Reply-To: <201808272317499067164@zte.com.cn> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel2=m.gmane.org@nongnu.org Sender: "Qemu-devel" List-Id: kvm.vger.kernel.org On Mon, Aug 27, 2018 at 11:17:49PM +0800, peng.hao2@zte.com.cn wrote: > >On Mon, Aug 27, 2018 at 04:25:00PM +0800, peng.hao2@zte.com.cn wrote: > >> >> On 25 Aug 2018, at 15:19, Peng Hao wrote: > >> >> > >> >> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c > >> >> index 0e60834..da73743 100644 > >> >> --- a/hw/pci-host/piix.c > >> >> +++ b/hw/pci-host/piix.c > >> >> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) > >> >> > >> >> sysbus_add_io(sbd, 0xcfc, &s->data_mem); > >> >> sysbus_init_ioports(sbd, 0xcfc, 4); > >> >> + > >> >> + /* register i440fx 0xcf8 port as coalesced pio */ > >> >> + memory_region_set_flush_coalesced(&s->data_mem); > >> >> + memory_region_add_coalescing(&s->conf_mem, 0, 4); > >> >> } > >> >> > >> >Is there a reason to not register this port as coalesced PIO also for Q35? > >> >In q35_host_realize()? > >> >If not, I would do that as an extra patch as part of this series. > >> Just as I mentioned in patch [0/4] , you can add pci->>host config port as coalesecd pio. I think it works for q35 port 0xcf8. > >> >-Liran > > > >What's the performance improvement for q35? > q35 also has the same pci-host config port 0xcf8 as piix. I test the coalesced pio for > q35 pci-host config port 0xcf8. It spent less VM-exit avg time from 3us to 0.6us. so pls include that patch too. piix is mostly feature frozen, piix only features aren't likely to be merged. > >-- > >MST