From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Emilio G. Cota" Subject: Re: [PATCH 11/35] target/i386: access cpu->interrupt_request with atomics Date: Wed, 19 Sep 2018 11:02:20 -0400 Message-ID: <20180919150220.GA28724@flamenco> References: <20180917163103.6113-1-cota@braap.org> <20180917163103.6113-12-cota@braap.org> <681e812b-43f2-04b2-f015-489b6154fec8@twiddle.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Paolo Bonzini , Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org, Eduardo Habkost To: Richard Henderson Return-path: Content-Disposition: inline In-Reply-To: <681e812b-43f2-04b2-f015-489b6154fec8@twiddle.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel2=m.gmane.org@nongnu.org Sender: "Qemu-devel" List-Id: kvm.vger.kernel.org On Tue, Sep 18, 2018 at 14:04:35 -0700, Richard Henderson wrote: > On 9/17/18 9:30 AM, Emilio G. Cota wrote: > > cpu_reset(cs); > > - cs->interrupt_request = sipi; > > + atomic_mb_set(&cs->interrupt_request, sipi); > > memcpy(&env->start_init_save, &save->start_init_save, > > Why does this need a memory barrier? > > Anyway, I think a bare mechanical conversion would be best > for the first patch and then extra barriers added separately > and with a description of why. Almost no corresponding read has a barrier so it's hard to justify this one. I'll drop it. Thanks, Emilio