From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
Thomas Gleixner <tglx@linutronix.de>,
Kees Cook <keescook@chromium.org>,
kvm@vger.kernel.org, KarimAllah Ahmed <karahmed@amazon.de>,
andrew.cooper3@citrix.com, "H. Peter Anvin" <hpa@zytor.com>,
Borislav Petkov <bp@suse.de>, David Woodhouse <dwmw@amazon.co.uk>
Subject: [PATCH 4.14 071/146] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features
Date: Tue, 4 Dec 2018 11:49:17 +0100 [thread overview]
Message-ID: <20181204103729.696978234@linuxfoundation.org> (raw)
In-Reply-To: <20181204103726.750894136@linuxfoundation.org>
4.14-stable review patch. If anyone has any objections, please let me know.
------------------
From: Konrad Rzeszutek Wilk konrad.wilk@oracle.com
commit 108fab4b5c8f12064ef86e02cb0459992affb30f upstream
Both AMD and Intel can have SPEC_CTRL_MSR for SSBD.
However AMD also has two more other ways of doing it - which
are !SPEC_CTRL MSR ways.
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Kees Cook <keescook@chromium.org>
Cc: kvm@vger.kernel.org
Cc: KarimAllah Ahmed <karahmed@amazon.de>
Cc: andrew.cooper3@citrix.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Link: https://lkml.kernel.org/r/20180601145921.9500-4-konrad.wilk@oracle.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/x86/kernel/cpu/bugs.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -535,17 +535,12 @@ static enum ssb_mitigation __init __ssb_
* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
* use a completely different MSR and bit dependent on family.
*/
- switch (boot_cpu_data.x86_vendor) {
- case X86_VENDOR_INTEL:
- case X86_VENDOR_AMD:
- if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
- x86_amd_ssb_disable();
- break;
- }
+ if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
+ x86_amd_ssb_disable();
+ else {
x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
- break;
}
}
next prev parent reply other threads:[~2018-12-04 10:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20181204103726.750894136@linuxfoundation.org>
2018-12-04 10:49 ` [PATCH 4.14 069/146] x86/bugs: Add AMDs variant of SSB_NO Greg Kroah-Hartman
2018-12-04 10:49 ` [PATCH 4.14 070/146] x86/bugs: Add AMDs SPEC_CTRL MSR usage Greg Kroah-Hartman
2018-12-04 10:49 ` Greg Kroah-Hartman [this message]
2018-12-04 10:50 ` [PATCH 4.14 121/146] x86/fpu: Disable bottom halves while loading FPU registers Greg Kroah-Hartman
2018-12-05 16:26 ` Jari Ruusu
2018-12-05 19:00 ` Borislav Petkov
2018-12-06 10:54 ` Greg Kroah-Hartman
2018-12-21 16:23 ` [PATCH v4.9 STABLE] " Sebastian Andrzej Siewior
2018-12-21 16:29 ` Greg Kroah-Hartman
2018-12-21 16:38 ` Sebastian Andrzej Siewior
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