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From: Marc Zyngier <marc.zyngier@arm.com>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>
Cc: kvm@vger.kernel.org,
	Richard Henderson <richard.henderson@linaro.org>,
	Masami Hiramatsu <mhiramat@kernel.org>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 04/11] arm64: KVM: Don't generate UNDEF when LORegion feature is present
Date: Thu,  7 Feb 2019 13:18:36 +0000	[thread overview]
Message-ID: <20190207131843.157210-5-marc.zyngier@arm.com> (raw)
In-Reply-To: <20190207131843.157210-1-marc.zyngier@arm.com>

We currently hide the LORegion feature, and generate an UNDEF
if the guest dares using the corresponding registers. This is
a bit extreme, as ARMv8.1 guarantees the feature to be present.

The guest should check the feature register before doing anything,
but we could also give the guest some slack (read "allow the
guest to be a bit stupid").

So instead of unconditionnaly deliver an exception, let's
only do it when the host doesn't support LORegion at all (or
when the feature has been sanitized out), and treat the registers
as RAZ/WI otherwise (with the exception of LORID_EL1 being RO).

Fixes: cc33c4e20185 ("arm64/kvm: Prohibit guest LOR accesses")
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
---
 arch/arm64/kvm/sys_regs.c | 42 +++++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e3e37228ae4e..86096774abcd 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -314,12 +314,29 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 		return read_zero(vcpu, p);
 }
 
-static bool trap_undef(struct kvm_vcpu *vcpu,
-		       struct sys_reg_params *p,
-		       const struct sys_reg_desc *r)
+/*
+ * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
+ * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
+ * system, these registers should UNDEF. LORID_EL1 being a RO register, we
+ * treat it separately.
+ */
+static bool trap_loregion(struct kvm_vcpu *vcpu,
+			  struct sys_reg_params *p,
+			  const struct sys_reg_desc *r)
 {
-	kvm_inject_undefined(vcpu);
-	return false;
+	u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
+	u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
+			 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
+
+	if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
+		kvm_inject_undefined(vcpu);
+		return false;
+	}
+
+	if (p->is_write && sr == SYS_LORID_EL1)
+		return write_to_read_only(vcpu, p, r);
+
+	return trap_raz_wi(vcpu, p, r);
 }
 
 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
@@ -1048,11 +1065,6 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)
 		if (val & ptrauth_mask)
 			kvm_debug("ptrauth unsupported for guests, suppressing\n");
 		val &= ~ptrauth_mask;
-	} else if (id == SYS_ID_AA64MMFR1_EL1) {
-		if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))
-			kvm_debug("LORegions unsupported for guests, suppressing\n");
-
-		val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
 	}
 
 	return val;
@@ -1338,11 +1350,11 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
 	{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 
-	{ SYS_DESC(SYS_LORSA_EL1), trap_undef },
-	{ SYS_DESC(SYS_LOREA_EL1), trap_undef },
-	{ SYS_DESC(SYS_LORN_EL1), trap_undef },
-	{ SYS_DESC(SYS_LORC_EL1), trap_undef },
-	{ SYS_DESC(SYS_LORID_EL1), trap_undef },
+	{ SYS_DESC(SYS_LORSA_EL1), trap_loregion },
+	{ SYS_DESC(SYS_LOREA_EL1), trap_loregion },
+	{ SYS_DESC(SYS_LORN_EL1), trap_loregion },
+	{ SYS_DESC(SYS_LORC_EL1), trap_loregion },
+	{ SYS_DESC(SYS_LORID_EL1), trap_loregion },
 
 	{ SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
 	{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
-- 
2.20.1

  parent reply	other threads:[~2019-02-07 13:18 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-07 13:18 [GIT PULL] KVM/ARM updates for 5.0-rc6 Marc Zyngier
2019-02-07 13:18 ` [PATCH 01/11] KVM: arm/arm64: vgic: Make vgic_irq->irq_lock a raw_spinlock Marc Zyngier
2019-02-07 13:18 ` [PATCH 02/11] KVM: arm/arm64: vgic: Make vgic_dist->lpi_list_lock " Marc Zyngier
2019-02-07 13:18 ` [PATCH 03/11] KVM: arm/arm64: vgic: Make vgic_cpu->ap_list_lock " Marc Zyngier
2019-02-07 13:18 ` Marc Zyngier [this message]
2019-02-07 13:18 ` [PATCH 05/11] KVM: arm/arm64: Reset the VCPU without preemption and vcpu state loaded Marc Zyngier
2019-03-04 16:30   ` Julien Grall
2019-03-04 17:06     ` Marc Zyngier
2019-03-04 17:31       ` Julien Grall
2019-03-04 17:37         ` Marc Zyngier
2019-02-07 13:18 ` [PATCH 06/11] arm/arm64: KVM: Allow a VCPU to fully reset itself Marc Zyngier
2019-02-07 13:18 ` [PATCH 07/11] arm/arm64: KVM: Don't panic on failure to properly reset system registers Marc Zyngier
2019-02-07 13:18 ` [PATCH 08/11] KVM: arm/arm64: vgic: Always initialize the group of private IRQs Marc Zyngier
2019-02-07 13:18 ` [PATCH 09/11] arm: KVM: Add missing kvm_stage2_has_pmd() helper Marc Zyngier
2019-02-07 13:18 ` [PATCH 10/11] KVM: arm64: Relax the restriction on using stage2 PUD huge mapping Marc Zyngier
2019-02-07 13:18 ` [PATCH 11/11] KVM: arm64: Forbid kprobing of the VHE world-switch code Marc Zyngier
2019-02-13 18:39 ` [GIT PULL] KVM/ARM updates for 5.0-rc6 Paolo Bonzini

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