From mboxrd@z Thu Jan  1 00:00:00 1970
From: Sean Christopherson <sean.j.christopherson@intel.com>
Subject: Re: [PATCH v2 1/7] KVM:VMX: Define CET VMCS fields and bits
Date: Fri, 8 Mar 2019 07:50:46 -0800
Message-ID: <20190308155046.GA2528@linux.intel.com>
References: <20190122205909.24165-1-weijiang.yang@intel.com>
 <20190122205909.24165-2-weijiang.yang@intel.com>
 <5a31eef0-2b6c-bdc2-c54b-5dc4cecf084d@redhat.com>
 <20190128103345.GA29895@local-michael-cet-test.sh.intel.com>
 <4d9a5393-163b-f32a-4657-cec54093ee88@redhat.com>
 <20190304185621.GG17120@linux.intel.com>
 <b519607c-a9d2-5b41-07dd-c8ca9ab53d3f@redhat.com>
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Cc: Yang Weijiang <weijiang.yang@intel.com>, rkrcmar@redhat.com,
        jmattson@google.com, linux-kernel@vger.kernel.org,
        kvm@vger.kernel.org, mst@redhat.com, yu-cheng.yu@intel.com,
        yi.z.zhang@intel.com, hjl.tools@gmail.com,
        Zhang Yi Z <yi.z.zhang@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
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On Fri, Mar 08, 2019 at 10:15:15AM +0100, Paolo Bonzini wrote:
> On 04/03/19 19:56, Sean Christopherson wrote:
> > On Tue, Jan 29, 2019 at 04:19:34PM +0100, Paolo Bonzini wrote:
> >> On 28/01/19 11:33, Yang Weijiang wrote:
> >>>> There is no code in this series to pass these fields to and from
> >>>> userspace, and also to save/restore U_CET, INT_SSP_TAB, PL0_SSP and
> >>>> PL3_SSP across context switches.
> >>>>
> >>> The kernel consumes these MSRs, please see kernel CET patch:
> >>> https://lkml.org/lkml/fancy/2018/11/20/225
> >>
> >> Still, even if the kernel saves these fields across context switch in
> >> XSAVE areas, KVM must support accesses to the MSRs from userspace, for
> >> example in order to perform live migration.
> >>
> >> For example, when reading/writing these in kvm_set_msr or
> >> kvm_get_msr_common, you would have to do a read/write from the host
> >> MSRs.  You also have to put kvm_load_guest_fpu/kvm_put_guest_fpu calls
> >> in __msr_io.
> > 
> > Paolo, can you elaborate on why KVM would read the host MSRs?  Wouldn't
> > kvm_{get,set}_msr() pull the values from the VMCS when necessary?
> 
> Not all MSRs are in the VMCS; IA32_U_CET and IA32_PL*_SSP are not.

Ah, "host MSRs" confused me.  I though you meant the host's version of
the MSRs, but you're saying do an XRSTORS to load the guest's FPU state
and then {RD,WR}MSR to pull the guest's value from hardware.