From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH 1/2] kvm/x86: Move MSR_K7_HWCR to svm.c Date: Mon, 25 Mar 2019 20:38:49 +0100 Message-ID: <20190325193821.GS12016@zn.tnic> References: <20190325171649.7311-1-bp@alien8.de> <20190325171649.7311-2-bp@alien8.de> <20190325182133.GG31069@linux.intel.com> <20190325183909.GQ12016@zn.tnic> <20190325192111.GH31069@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Cc: KVM , Joerg Roedel , Paolo Bonzini , Radim =?utf-8?B?S3LEjW3DocWZ?= , Tom Lendacky , Tony Luck , Yazen Ghannam , LKML To: Sean Christopherson Return-path: Content-Disposition: inline In-Reply-To: <20190325192111.GH31069@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Mon, Mar 25, 2019 at 12:21:11PM -0700, Sean Christopherson wrote: > Generally speaking, the goal is to support cross-vendor VMs without having > to modify the guest kernel, i.e. exact emulation is out of scope. This > means "emulating" cross-vendor MSRs that the guest expects to exist to the > point where the guest won't explode, e.g. in the case of MSR_K7_HWCR, Linux > expects the MSR to exist on all AMD platforms and AFAICT will die during > boot if it doesn't. > > The rule of thumb for "what MSRs can a guest reasonably expect to exist" > is fluid. Ok, I'll keep it in the common MSR accessors in the next version. Thx for confirming what I was suspecting. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.