From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Christopherson Subject: Re: [RFC PATCH v4 4/8] KVM:VMX: Pass through host CET related MSRs to Guest. Date: Tue, 2 Apr 2019 13:27:33 -0700 Message-ID: <20190402202733.GI31303@linux.intel.com> References: <20190318150351.15550-1-weijiang.yang@intel.com> <20190318150351.15550-5-weijiang.yang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: pbonzini@redhat.com, kvm@vger.kernel.org, mst@redhat.com, rkrcmar@redhat.com, jmattson@google.com, linux-kernel@vger.kernel.org, yu-cheng.yu@intel.com, Zhang Yi Z To: Yang Weijiang Return-path: Content-Disposition: inline In-Reply-To: <20190318150351.15550-5-weijiang.yang@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Mon, Mar 18, 2019 at 11:03:47PM +0800, Yang Weijiang wrote: > The CET runtime settings, i.e., CET state control bits(IA32_U_CET/ > IA32_S_CET), CET SSP(IA32_PL3_SSP/IA32_PL0_SSP) and SSP table address > (IA32_INTERRUPT_SSP_TABLE_ADDR) are task/thread specific, therefore, > OS needs to save/restore the states properly during context switch, > e.g., task/thread switching, interrupt/exception handling, it uses > xsaves/xrstors to achieve that. > > The difference between VMCS CET area fields and xsave CET area, is that > the former is for state retention during Guest/Host context > switch while the latter is for state retention during OS execution. > > Linux currently doesn't support CPL1 and CPL2, so SSPs for these level > are skipped here. > > Signed-off-by: Zhang Yi Z > Signed-off-by: Yang Weijiang > --- > arch/x86/kvm/vmx.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index 53cef5a3db96..28b8ac027bd7 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -11774,6 +11774,7 @@ static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) > static void vmx_cpuid_update(struct kvm_vcpu *vcpu) > { > struct vcpu_vmx *vmx = to_vmx(vcpu); > + unsigned long *msr_bitmap; > > if (cpu_has_secondary_exec_ctrls()) { > vmx_compute_secondary_exec_control(vmx); > @@ -11791,6 +11792,18 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu) > nested_vmx_cr_fixed1_bits_update(vcpu); > nested_vmx_entry_exit_ctls_update(vcpu); > } > + > + msr_bitmap = vmx->vmcs01.msr_bitmap; > + > + if (guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) || > + guest_cpuid_has(vcpu, X86_FEATURE_IBT)) { > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_U_CET, MSR_TYPE_RW); > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_S_CET, MSR_TYPE_RW); > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_INT_SSP_TAB, MSR_TYPE_RW); > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_PL0_SSP, MSR_TYPE_RW); I thought we had agreed to pass-through PL1 and PL2, or am I misremembering? > + vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_PL3_SSP, MSR_TYPE_RW); > + } > + > } > > static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) > -- > 2.17.1 >