From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCCC4C10F0E for ; Mon, 15 Apr 2019 20:00:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 92EBE2070D for ; Mon, 15 Apr 2019 20:00:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729035AbfDOUAg (ORCPT ); Mon, 15 Apr 2019 16:00:36 -0400 Received: from mga06.intel.com ([134.134.136.31]:12921 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728548AbfDOUAg (ORCPT ); Mon, 15 Apr 2019 16:00:36 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Apr 2019 13:00:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,354,1549958400"; d="scan'208";a="131627527" Received: from sjchrist-coffee.jf.intel.com ([10.54.74.181]) by orsmga007.jf.intel.com with ESMTP; 15 Apr 2019 13:00:35 -0700 From: Sean Christopherson To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Cc: kvm@vger.kernel.org, Nadav Amit Subject: [kvm-unit-tests PATCH] x86: apic: Preserve APIC base and BSP bits during x2APIC tests Date: Mon, 15 Apr 2019 13:00:34 -0700 Message-Id: <20190415200034.6839-1-sean.j.christopherson@intel.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org ...and reset to xAPIC mode unless x2APIC was already enabled. Make the "APIC disabled to APIC enabled" a reported subtest so that it's (slightly) more obviously that the vCPU is transitioning back to legacy xAPIC mode and that the APIC was disabled via a previous subtest, i.e. won't fault due to an illegal transition. Note, reset_apic() is overkill since the vCPU is already in legacy xAPIC mode, i.e. the test really just needs "apic_ops = &xapic_ops;". But two MSR accesses are negligible in the grand scheme and using reset_apic() is less reliant on the exact flow of the test. Reported-by: Nadav Amit Signed-off-by: Sean Christopherson --- x86/apic.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/x86/apic.c b/x86/apic.c index 51744cf..7f711c0 100644 --- a/x86/apic.c +++ b/x86/apic.c @@ -69,32 +69,44 @@ static void do_write_apicbase(void *data) static bool test_write_apicbase_exception(u64 data) { - data |= APIC_DEFAULT_PHYS_BASE | APIC_BSP; return test_for_exception(GP_VECTOR, do_write_apicbase, &data); } static void test_enable_x2apic(void) { + u64 orig_apicbase = rdmsr(MSR_IA32_APICBASE); + u64 apicbase; + if (enable_x2apic()) { printf("x2apic enabled\n"); + apicbase = orig_apicbase & ~(APIC_EN | APIC_EXTD); report("x2apic enabled to invalid state", - test_write_apicbase_exception(APIC_EXTD)); + test_write_apicbase_exception(apicbase | APIC_EXTD)); report("x2apic enabled to apic enabled", - test_write_apicbase_exception(APIC_EN)); + test_write_apicbase_exception(apicbase | APIC_EN)); report("x2apic enabled to disabled state", - !test_write_apicbase_exception(0)); + !test_write_apicbase_exception(apicbase | 0)); report("disabled to invalid state", - test_write_apicbase_exception(APIC_EXTD)); + test_write_apicbase_exception(apicbase | APIC_EXTD)); report("disabled to x2apic enabled", - test_write_apicbase_exception(APIC_EN | APIC_EXTD)); + test_write_apicbase_exception(apicbase | APIC_EN | APIC_EXTD)); - wrmsr(MSR_IA32_APICBASE, APIC_EN); + report("apic disabled to apic enabled", + !test_write_apicbase_exception(apicbase | APIC_EN)); report("apic enabled to invalid state", - test_write_apicbase_exception(APIC_EXTD)); + test_write_apicbase_exception(apicbase | APIC_EXTD)); - wrmsr(MSR_IA32_APICBASE, APIC_EN | APIC_EXTD); + if (orig_apicbase & APIC_EXTD) + enable_x2apic(); + else + reset_apic(); + + /* + * Disabling the APIC resets various APIC registers, restore them to + * their desired values. + */ apic_write(APIC_SPIV, 0x1ff); } else { printf("x2apic not detected\n"); -- 2.21.0