Re: [PATCH -v5.1] x86/kvm: Implement HWCR support

Paolo Bonzini
2019-04-18T16:34:55Z

On 18/04/19 14:28, Borislav Petkov wrote:
> The hardware configuration register has some useful bits which can be
> used by guests. Implement McStatusWrEn which can be used by guests when
> injecting MCEs with the in-kernel mce-inject module.
>
> For that, we need to set bit 18 - McStatusWrEn - first, before writing
> the MCi_STATUS registers (otherwise we #GP).
>
> Add the required machinery to do so.

Just one little thing missing:

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index eb49d2cee68a..6e23343c6b36 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1172,6 +1172,8 @@ bool kvm_rdpmc(struct kvm_vcpu *vcpu)
MSR_MISC_FEATURES_ENABLES,
MSR_AMD64_VIRT_SPEC_CTRL,
MSR_IA32_POWER_CTL,
+
+ MSR_K7_HWCR,
};

static unsigned num_emulated_msrs;

Queued with this change.

Paolo

>
> Signed-off-by: Borislav Petkov <bp@suse.de>
> Cc: Jim Mattson <jmattson@google.com>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: KVM <kvm@vger.kernel.org>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Radim Krčmář <rkrcmar@redhat.com>
> Cc: Sean Christopherson <sean.j.christopherson@intel.com>
> Cc: Tom Lendacky <thomas.lendacky@amd.com>
> Cc: Tony Luck <tony.luck@intel.com>
> Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>
> ---
> arch/x86/include/asm/kvm_host.h | 3 +++
> arch/x86/kvm/x86.c | 33 +++++++++++++++++++++++++++------
> 2 files changed, 30 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 159b5988292f..541c431df806 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -780,6 +780,9 @@ struct kvm_vcpu_arch {
>
> /* Flush the L1 Data cache for L1TF mitigation on VMENTER */
> bool l1tf_flush_l1d;
> +
> + /* AMD MSRC001_0015 Hardware Configuration */
> + u64 msr_hwcr;
> };
>
> struct kvm_lpage_info {
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 099b851dabaf..10f6acc6494c 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -2273,6 +2273,18 @@ static void kvmclock_sync_fn(struct work_struct *work)
> KVMCLOCK_SYNC_PERIOD);
> }
>
> +/*
> + * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
> + */
> +static bool can_set_mci_status(struct kvm_vcpu *vcpu)
> +{
> + /* McStatusWrEn enabled? */
> + if (guest_cpuid_is_amd(vcpu))
> + return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
> +
> + return false;
> +}
> +
> static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> {
> u64 mcg_cap = vcpu->arch.mcg_cap;
> @@ -2304,9 +2316,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> if ((offset & 0x3) == 0 &&
> data != 0 && (data | (1 << 10)) != ~(u64)0)
> return -1;
> - if (!msr_info->host_initiated &&
> - (offset & 0x3) == 1 && data != 0)
> - return -1;
> +
> + /* MCi_STATUS */
> + if ((offset & 0x3) == 1 && !msr_info->host_initiated) {
> + if (!can_set_mci_status(vcpu))
> + return -1;
> + }
> +
> vcpu->arch.mce_banks[offset] = data;
> break;
> }
> @@ -2455,8 +2471,11 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> data &= ~(u64)0x40; /* ignore flush filter disable */
> data &= ~(u64)0x100; /* ignore ignne emulation enable */
> data &= ~(u64)0x8; /* ignore TLB cache disable */
> - data &= ~(u64)0x40000; /* ignore Mc status write enable */
> - if (data != 0) {
> +
> + /* Handle McStatusWrEn */
> + if (data == BIT_ULL(18)) {
> + vcpu->arch.msr_hwcr = data;
> + } else if (data != 0) {
> vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
> data);
> return 1;
> @@ -2730,7 +2749,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> case MSR_K8_SYSCFG:
> case MSR_K8_TSEG_ADDR:
> case MSR_K8_TSEG_MASK:
> - case MSR_K7_HWCR:
> case MSR_VM_HSAVE_PA:
> case MSR_K8_INT_PENDING_MSG:
> case MSR_AMD64_NB_CFG:
> @@ -2894,6 +2912,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> case MSR_MISC_FEATURES_ENABLES:
> msr_info->data = vcpu->arch.msr_misc_features_enables;
> break;
> + case MSR_K7_HWCR:
> + msr_info->data = vcpu->arch.msr_hwcr;
> + break;
> default:
> if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
> return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
> -- 2.21.0

Queued, thanks.