From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0448DC433FF for ; Fri, 9 Aug 2019 07:09:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CFE6B2171F for ; Fri, 9 Aug 2019 07:09:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565334544; bh=xLxdfwVAGkfE8tvcBwKoTVIh2by4p0SPpkfK40di0ZA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=b3ilt0AdETQ4SNXoLcm+2qDeRRcEaWWgYb0qCKCUVMo15joGY36AFKgFs2DpTTZp/ MlrniwgIr7AFbJt7veiJUa5YlzsU6wzTi220yrICJmTi2222vhf1/nq0Fm+mCy6Bxl T9wjSjkFUJyTVrUkWKJj4qxCwSDI7pEephGcJUs4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405691AbfHIHJD (ORCPT ); Fri, 9 Aug 2019 03:09:03 -0400 Received: from inca-roads.misterjones.org ([213.251.177.50]:43265 "EHLO inca-roads.misterjones.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725954AbfHIHJD (ORCPT ); Fri, 9 Aug 2019 03:09:03 -0400 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:AES256-GCM-SHA384:256) (Exim 4.80) (envelope-from ) id 1hvz1H-0002zE-LG; Fri, 09 Aug 2019 09:08:59 +0200 Date: Fri, 9 Aug 2019 08:08:56 +0100 From: Marc Zyngier To: Alexandru Elisei Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, andre.przywara@arm.com Subject: Re: [PATCH] KVM: arm/arm64: vgic: Reevaluate level sensitive interrupts on enable Message-ID: <20190809080856.61ab570b@why> In-Reply-To: <1565171600-11082-1-git-send-email-alexandru.elisei@arm.com> References: <1565171600-11082-1-git-send-email-alexandru.elisei@arm.com> Organization: Approximate X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, andre.przywara@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, 7 Aug 2019 10:53:20 +0100 Alexandru Elisei wrote: > A HW mapped level sensitive interrupt asserted by a device will not be put > into the ap_list if it is disabled at the VGIC level. When it is enabled > again, it will be inserted into the ap_list and written to a list register > on guest entry regardless of the state of the device. > > We could argue that this can also happen on real hardware, when the command > to enable the interrupt reached the GIC before the device had the chance to > de-assert the interrupt signal; however, we emulate the distributor and > redistributors in software and we can do better than that. > > Signed-off-by: Alexandru Elisei > --- > virt/kvm/arm/vgic/vgic-mmio.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c > index 3ba7278fb533..44efc2ff863f 100644 > --- a/virt/kvm/arm/vgic/vgic-mmio.c > +++ b/virt/kvm/arm/vgic/vgic-mmio.c > @@ -113,6 +113,22 @@ void vgic_mmio_write_senable(struct kvm_vcpu *vcpu, > struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); > > raw_spin_lock_irqsave(&irq->irq_lock, flags); > + if (vgic_irq_is_mapped_level(irq)) { > + bool was_high = irq->line_level; > + > + /* > + * We need to update the state of the interrupt because > + * the guest might have changed the state of the device > + * while the interrupt was disabled at the VGIC level. > + */ > + irq->line_level = vgic_get_phys_line_level(irq); > + /* > + * Deactivate the physical interrupt so the GIC will let > + * us know when it is asserted again. > + */ > + if (!irq->active && was_high && !irq->line_level) > + vgic_irq_set_phys_active(irq, false); > + } > irq->enabled = true; > vgic_queue_irq_unlock(vcpu->kvm, irq, flags); > Applied, thanks. M. -- Without deviation from the norm, progress is not possible.