Re: [PATCH v7 1/7] KVM: CPUID: Fix IA32_XSS support in CPUID(0xd,i) enumeration

Sean Christopherson
2019-10-22T19:46:20Z

On Fri, Oct 18, 2019 at 09:28:09AM +0800, Yang Weijiang wrote:
> On Thu, Oct 17, 2019 at 12:46:22PM -0700, Sean Christopherson wrote:
> > On Wed, Oct 02, 2019 at 10:26:10AM -0700, Jim Mattson wrote:
> > > > + entry->eax = 0;
> > > > + entry->ebx = 0;
> > > > + entry->ecx = 0;
> > > > + entry->edx = 0;
> > > > + return;
> > > > + }
> > > > + if (entry->ecx)
> > > > + entry->ebx = 0;
> > >
> > > This seems to back up my claims above regarding the EBX output for
> > > cases 0 and 1, but aside from those subleaves, is this correct? For
> > > subleaves > 1, ECX bit 1 can be set for extended state components that
> > > need to be cache-line aligned. Such components could map to a valid
> > > bit in XCR0 and have a non-zero offset from the beginning of the
> > > non-compacted XSAVE area.
> > >
> > > > + entry->edx = 0;
> > >
> > > This seems too aggressive. See my comments above regarding EDX outputs
> > > for cases 0 and 1.
> > >
> Sean, I don't know how to deal with entry->edx here as SDM says it's
> reserved for valid subleaf.

The SDM also states:

Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0.
XCR0[n+32] can be set to 1 only if EDX[n] is 1.

the second part, "Bits 31 - 00: Reserved" is at best superfluous, e.g. it
could be interpreted as saying that XCR0[63:32] are currently reserved,
and at worst the extra qualifier is an SDM bug and should be removed.

TL;DR: Ignore the blurb about the bits being reserved.