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[142.162.113.180]) by smtp.gmail.com with ESMTPSA id l14sm2995037qkj.61.2019.11.08.06.40.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Nov 2019 06:40:54 -0800 (PST) Received: from jgg by mlx.ziepe.ca with local (Exim 4.90_1) (envelope-from ) id 1iT5RW-0003PI-Ar; Fri, 08 Nov 2019 10:40:54 -0400 Date: Fri, 8 Nov 2019 10:40:54 -0400 From: Jason Gunthorpe To: Jiri Pirko , Ertman@ziepe.ca, David M , gregkh@linuxfoundation.org Cc: Jakub Kicinski , Parav Pandit , alex.williamson@redhat.com, davem@davemloft.net, kvm@vger.kernel.org, netdev@vger.kernel.org, saeedm@mellanox.com, kwankhede@nvidia.com, leon@kernel.org, cohuck@redhat.com, jiri@mellanox.com, linux-rdma@vger.kernel.org, Or Gerlitz Subject: Re: [PATCH net-next 00/19] Mellanox, mlx5 sub function support Message-ID: <20191108144054.GC10956@ziepe.ca> References: <20191107160448.20962-1-parav@mellanox.com> <20191107153234.0d735c1f@cakuba.netronome.com> <20191108121233.GJ6990@nanopsycho> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191108121233.GJ6990@nanopsycho> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Fri, Nov 08, 2019 at 01:12:33PM +0100, Jiri Pirko wrote: > Thu, Nov 07, 2019 at 09:32:34PM CET, jakub.kicinski@netronome.com wrote: > >On Thu, 7 Nov 2019 10:04:48 -0600, Parav Pandit wrote: > >> Mellanox sub function capability allows users to create several hundreds > >> of networking and/or rdma devices without depending on PCI SR-IOV support. > > > >You call the new port type "sub function" but the devlink port flavour > >is mdev. > > > >As I'm sure you remember you nacked my patches exposing NFP's PCI > >sub functions which are just regions of the BAR without any mdev > >capability. Am I in the clear to repost those now? Jiri? > > Well question is, if it makes sense to have SFs without having them as > mdev? I mean, we discussed the modelling thoroughtly and eventually we > realized that in order to model this correctly, we need SFs on "a bus". > Originally we were thinking about custom bus, but mdev is already there > to handle this. Did anyone consult Greg on this? The new intel driver has been having a very similar discussion about how to model their 'multi function device' ie to bind RDMA and other drivers to a shared PCI function, and I think that discussion settled on adding a new bus? Really these things are all very similar, it would be nice to have a clear methodology on how to use the device core if a single PCI device is split by software into multiple different functional units and attached to different driver instances. Currently there is alot of hacking in this area.. And a consistent scheme might resolve the ugliness with the dma_ops wrappers. We already have the 'mfd' stuff to support splitting platform devices, maybe we need to create a 'pci-mfd' to support splitting PCI devices? I'm not really clear how mfd and mdev relate, I always thought mdev was strongly linked to vfio. At the very least if it is agreed mdev should be the vehicle here, then it should also be able to solve the netdev/rdma hookup problem too. Jason