From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB3BEC3F2D1 for ; Wed, 4 Mar 2020 16:19:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9E740215A4 for ; Wed, 4 Mar 2020 16:19:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388040AbgCDQTN (ORCPT ); Wed, 4 Mar 2020 11:19:13 -0500 Received: from mga14.intel.com ([192.55.52.115]:25026 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726764AbgCDQTN (ORCPT ); Wed, 4 Mar 2020 11:19:13 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Mar 2020 08:19:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,514,1574150400"; d="scan'208";a="439182749" Received: from sjchrist-coffee.jf.intel.com (HELO linux.intel.com) ([10.54.74.202]) by fmsmga005.fm.intel.com with ESMTP; 04 Mar 2020 08:19:12 -0800 Date: Wed, 4 Mar 2020 08:19:12 -0800 From: Sean Christopherson To: Peter Feiner Cc: Jim Mattson , kvm list Subject: Re: Nested virtualization and software page walks in the L1 hypervsior Message-ID: <20200304161912.GC21662@linux.intel.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, Mar 03, 2020 at 04:22:57PM -0800, Peter Feiner wrote: > On Sat, Feb 29, 2020 at 2:31 PM Jim Mattson wrote: > > > > Peter Feiner asked me an intriguing question the other day. If you > > have a hypervisor that walks its guest's x86 page tables in software > > during emulation, how can you make that software page walk behave > > exactly like a hardware page walk? In particular, when the hypervisor > > is running as an L1 guest, how is it possible to write the software > > page walk so that accesses to L2's x86 page tables are treated as > > reads if L0 isn't using EPT A/D bits, but they're treated as writes if > > L0 is using EPT A/D bits? (Paravirtualization is not allowed.) > > > > It seems to me that this behavior isn't virtualizable. Am I wrong? > > Jim, I thought about this some more after talking to you. I think it's > entirely moot what L0 sees so long as L1 and L2 work correctly. So, > the question becomes, is there anything that L0 could possibly rely on > this behavior for? My first thought was dirty tracking, but that's not > a problem because *writes* to the L2 x86 page tables' A/D bits will > still be intercepted by L0. The missing D bit on a guest page that > doesn't actually change doesn't matter :-) Ya. The hardware behavior of setting the Dirty bit is effectively a spurious update. Not emulating that behavior is arguably a good thing :-). Presumably, the EPT walks are overzealous in treating IA32 page walks as writes to allow for simpler hardware implementations, e.g. the mechanism to handle A/D bit updates doesn't need to handle the case where setting an A/D bit in an IA32 page walk would also trigger an D bit update for the associated EPT walk.