From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35378C433EA for ; Tue, 14 Jul 2020 12:14:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 131752236F for ; Tue, 14 Jul 2020 12:14:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728548AbgGNMOR (ORCPT ); Tue, 14 Jul 2020 08:14:17 -0400 Received: from 8bytes.org ([81.169.241.247]:52918 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728376AbgGNMLA (ORCPT ); Tue, 14 Jul 2020 08:11:00 -0400 Received: from cap.home.8bytes.org (p5b006776.dip0.t-ipconnect.de [91.0.103.118]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by theia.8bytes.org (Postfix) with ESMTPSA id E55FFF8C; Tue, 14 Jul 2020 14:10:56 +0200 (CEST) From: Joerg Roedel To: x86@kernel.org Cc: Joerg Roedel , Joerg Roedel , hpa@zytor.com, Andy Lutomirski , Dave Hansen , Peter Zijlstra , Jiri Slaby , Dan Williams , Tom Lendacky , Juergen Gross , Kees Cook , David Rientjes , Cfir Cohen , Erdem Aktas , Masami Hiramatsu , Mike Stunes , Sean Christopherson , Martin Radev , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, virtualization@lists.linux-foundation.org Subject: [PATCH v4 44/75] x86/sev-es: Allocate and setup IST entry for #VC Date: Tue, 14 Jul 2020 14:08:46 +0200 Message-Id: <20200714120917.11253-45-joro@8bytes.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200714120917.11253-1-joro@8bytes.org> References: <20200714120917.11253-1-joro@8bytes.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Joerg Roedel Allocate IST entry number 4 for the #VC handler and setup it up in the per-cpu TSS. This will setup the TSS for all CPUs before they even start, so that the boot-code for secondary CPUs can handle #VC exceptions. Signed-off-by: Joerg Roedel --- arch/x86/include/asm/page_64_types.h | 1 + arch/x86/kernel/sev-es.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h index 288b065955b7..d0c6c10c18a0 100644 --- a/arch/x86/include/asm/page_64_types.h +++ b/arch/x86/include/asm/page_64_types.h @@ -28,6 +28,7 @@ #define IST_INDEX_NMI 1 #define IST_INDEX_DB 2 #define IST_INDEX_MCE 3 +#define IST_INDEX_VC 4 /* * Set __PAGE_OFFSET to the most negative possible address + diff --git a/arch/x86/kernel/sev-es.c b/arch/x86/kernel/sev-es.c index 64002d86a237..d415368f16ec 100644 --- a/arch/x86/kernel/sev-es.c +++ b/arch/x86/kernel/sev-es.c @@ -56,11 +56,13 @@ static void __init sev_es_setup_vc_stacks(int cpu) { struct sev_es_runtime_data *data; struct cpu_entry_area *cea; + struct tss_struct *tss; unsigned long vaddr; phys_addr_t pa; data = per_cpu(runtime_data, cpu); cea = get_cpu_entry_area(cpu); + tss = per_cpu_ptr(&cpu_tss_rw, cpu); /* Map #VC IST stack */ vaddr = CEA_ESTACK_BOT(&cea->estacks, VC); @@ -71,6 +73,9 @@ static void __init sev_es_setup_vc_stacks(int cpu) vaddr = CEA_ESTACK_BOT(&cea->estacks, VC2); pa = __pa(data->fallback_stack); cea_set_pte((void *)vaddr, pa, PAGE_KERNEL); + + /* Set IST entry in TSS */ + tss->x86_tss.ist[IST_INDEX_VC] = CEA_ESTACK_TOP(&cea->estacks, VC); } /* Needed in vc_early_forward_exception */ -- 2.27.0