From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E38FC4363A for ; Mon, 26 Oct 2020 14:22:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F14C222202 for ; Mon, 26 Oct 2020 14:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1780805AbgJZOWG (ORCPT ); Mon, 26 Oct 2020 10:22:06 -0400 Received: from foss.arm.com ([217.140.110.172]:40792 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1780743AbgJZOWF (ORCPT ); Mon, 26 Oct 2020 10:22:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FD4530E; Mon, 26 Oct 2020 07:22:05 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.56.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E35753F68F; Mon, 26 Oct 2020 07:22:03 -0700 (PDT) Date: Mon, 26 Oct 2020 14:22:01 +0000 From: Mark Rutland To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kernel-team@android.com, Will Deacon Subject: Re: [PATCH 07/11] KVM: arm64: Inject AArch64 exceptions from HYP Message-ID: <20201026142201.GH12454@C02TD0UTHF1T.local> References: <20201026133450.73304-1-maz@kernel.org> <20201026133450.73304-8-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201026133450.73304-8-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, Oct 26, 2020 at 01:34:46PM +0000, Marc Zyngier wrote: > Move the AArch64 exception injection code from EL1 to HYP, leaving > only the ESR_EL1 updates to EL1. In order to come with the differences > between VHE and nVHE, two set of system register accessors are provided. > > SPSR, ELR, PC and PSTATE are now completely handled in the hypervisor. > > Signed-off-by: Marc Zyngier > void kvm_inject_exception(struct kvm_vcpu *vcpu) > { > + switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) { > + case KVM_ARM64_EXCEPT_AA64_EL1_SYNC: > + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync); > + break; > + case KVM_ARM64_EXCEPT_AA64_EL1_IRQ: > + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_irq); > + break; > + case KVM_ARM64_EXCEPT_AA64_EL1_FIQ: > + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_fiq); > + break; > + case KVM_ARM64_EXCEPT_AA64_EL1_SERR: > + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_serror); > + break; > + default: > + /* EL2 are unimplemented until we get NV. One day. */ > + break; > + } > } Huh, we're going to allow EL1 to inject IRQ/FIQ/SERROR *exceptions* directly, rather than pending those via HCR_EL2.{VI,VF,VSE}? We never used to have code to do that. If we're going to support that we'll need to check against the DAIF bits to make sure we don't inject an exception that can't be architecturally taken. I guess we'll tighten that up along with the synchronous exception checks, but given those three cases aren't needed today it might be worth removing them from the switch for now and/or adding a comment to that effect. Thanks, Mark.